HDL-Optimized Filters and Transforms
Choose blocks or System objects to create HDL-optimized hardware system
designs
These DSP HDL Toolbox™ blocks and System objects implement hardware-friendly architectures and support HDL code generation when used with HDL Coder™. These blocks and System objects also have high-throughput streaming interfaces, hardware control signals, and options to select different hardware implementations of their algorithms.
Blocks
FFT | Compute fast Fourier transform (FFT) |
IFFT | Compute inverse fast Fourier transform (IFFT) |
Channelizer | Polyphase filter bank and fast Fourier transform |
Channel Synthesizer | Combine narrowband signals into multichannel signal |
Discrete FIR Filter | Finite-impulse response filter |
Biquad Filter | Biquadratic IIR (SOS) filter |
LMS Filter | Minimize error between observed and desired signals |
Farrow Rate Converter | Polynomial sample-rate converter |
FIR Decimator | Finite impulse response (FIR) decimation filter |
FIR Interpolator | Finite impulse response (FIR) interpolation filter |
CIC Decimator | Decimate signal using CIC filter |
CIC Interpolator | Interpolate signal using CIC filter |
FIR Rate Converter | Upsample, filter, and downsample input signal |
NCO | Generate real or complex sinusoidal signals |
Complex to Magnitude-Angle | Compute magnitude and phase angle of complex signal using CORDIC algorithm |
Downsampler | Downsample by removing data samples between input samples |
Upsampler | Upsample by adding zeros between input samples |
Objects
Topics
- High-Throughput HDL Algorithms
Choose a block that supports frame-based processing for HDL code generation.
- Hardware Control Signals
Hardware control signals such as valid and reset used by DSP HDL Toolbox blocks.
- FIR Filter Architectures for FPGAs and ASICs
Learn how DSP HDL Toolbox blocks implement hardware-friendly filter architectures.
- Control Data Rate Using Ready Signal
Implement backpressure and regulate output rate in an interpolator system.