HDL Implementation of Four Channel Synthesizer and Channelizer

This example shows how to synthesize a series of four stereo signals into a broadband signal using a channel synthesizer and how to split the synthesized broadband signal into four individual narrowband signals using a channelizer. The Simulink® model in this example contains a Synthesizer Channelizer subsystem with Channel Synthesizer and Channelizer blocks. These blocks support HDL code generation.

Data Source

Use these stereo signals as model inputs.

• FunkyDrums.mp3

• SoftGuitar.mp3

• RockDrums.mp3

• RockGuitar.mp3

Each stereo signal has two samples. The two channels in the model represent the left and right channels of a stereo signal. To store the channels of a stereo signal, convert each signal into a complex signal, multiplex, and then transpose to form a 1-by-2 vector.

Model Structure

Open the model.

model = 'HDLSynthesizerChannelizer';
open_system(model);

Model Parameters

The InitFcn callback sets up the model. To access the InitFcn callback, right-click the model, click Model Properties, open the Callbacks tab, and then click InitFcn. In the Channelizer block, set the Number of frequency bands parameter to 4. Each band has one FIR filter and each FIR filter has 24 taps, so the model has total of 96 filter taps. The designMultirateFIR function designs a multirate FIR filter and generates the filter coefficients. Set the number of taps per band and stopband attenuation. Calculate the filter coefficients by using the designMultiRateFIR function.

M = 4;                                       % number of frequency bands
P = 24;                                      % number of taps per band
Astop = 120;                                 % stop band attenuation
b = designMultirateFIR(1,M,ceil(P/2),Astop); % filter coefficients

Synthesizer and Channelizer

The Channel Synthesizer block synthesizes the input signals into a single broadband signal of size 4-by-1 by using an FFT-based synthesis filter bank. The model passes this signal to the Channelizer block. The Channelizer block splits the broadband input signal into four narrowband output signals. The output of the Channelizer block is a 1-by-4 vector, where each channel represents a narrowband.

Open the Synthesizer Channelizer subsystem.

open_system([model '/Synthesizer Channelizer']);

View the spectra of the input, synthesized signal, channelized signal, and synthesized-channelized output signal. The Synthesized Spectrum window shows the spectrum of the broadband signal. The Channelized Spectrum window shows the spectra of the four narrowband signals. The input and output spectra match for any selected signal.

open_system([model '/Control Scope']);
sim(model)

Audio Capture

Collect the output samples and reproduce the audio.

% Create a |dsp.AudioFileReader| object with default settings.
fileReader = dsp.AudioFileReader('output.ogg');

% Return a structure containing information about the audio file.
fileInfo = audioinfo('output.ogg');

% Create an |audioDeviceWriter| object and specify the sample rate.
deviceWriter = audioDeviceWriter('SampleRate',fileInfo.SampleRate);

% Reduce the computational load of initialization in the audio stream loop.
setup(deviceWriter,zeros(fileReader.SamplesPerFrame,fileInfo.NumChannels));

% In the audio stream loop, read the audio signal frame from the file and
% write the frame to your device.
while ~isDone(fileReader)
audioData = fileReader();
deviceWriter(audioData);
end

% Close the input file and release the device.
release(fileReader);
release(deviceWriter);

% Save and close the model.
open_system([model '/Control Scope']);
close_system(model,0)

HDL Code Generation and FPGA Implementation

To generate the HDL code for this example, you must have the HDL Coder™ product. Generate HDL code and an HDL testbench for the Synthesizer Channelizer subsystem. Synthesize this subsystem on a Xilinx® Zynq®-7000 ZC706 evaluation board. The table shows the post-place-and-route resource utilization results. The design meets the timing requirement with a clock frequency of 191.4 MHz. The resources and frequencies vary with the parameter values that you select in the block mask.

T = table(...
    categorical({'LUTs'; 'Slice Registers'; 'DSPs'}),...
    categorical({'1215'; '2861'; '384'}),...
    'VariableNames',{'Resource','Usage'})

T =

  3x2 table

       Resource        Usage
    _______________    _____

    LUTs               1215 
    Slice Registers    2861 
    DSPs               384