SoC Blockset™ enables simulation and evaluation of shared memory transactions in Simulink®. To include a memory system in your SoC model, configure a memory controller for the desired number of memory channels, and then connect the controller to memory channel blocks for arbitrating and handling memory traffic.
SoC Blockset enables the simulation and evaluation of shared memory transactions in Simulink. Visualize post-simulation performance and bandwidth metrics before deploying to SoC device by using the Logic Analyzer app.
|Memory Channel||Stream data through a memory channel|
|Memory Controller||Arbitrate memory transactions for one or more Memory Channel blocks|
|Memory Traffic Generator||Generate traffic towards memory controller|
|Register Channel||Timing model for transfer of register values|
|Interrupt Channel||Send interrupt to processor from hardware|
|AXI4 Master Sink||Receive random access memory data|
|AXI4 Master Source||Generate random access memory data|
|Stream Data Sink||Receive continuous stream data|
|Stream Data Source||Generate continuous stream data|
|SoC Bus Selector||Convert bus to control signals|
|SoC Bus Creator||Convert control signals to bus|
|Stream FIFO||Control backpressure between hardware logic and upstream data interface|
|Stream Connector||Connect two IPs with data streaming interfaces|
|IP Core Register Read||Model register writes from software to hardware|
|Logic Analyzer||Visualize, measure, and analyze transitions and states over time|
|Memory Mapper||Configure memory map for SoC application|
Introduction to memory and register transfers.
Supported memory channel protocols and control signals.
How to design your model for AXI4-Stream vector or scalar interface generation.
Description of AXI4 Master protocol, and how you can design your model for IP core generation with AXI4-Master interfaces.
How to design your model for IP core generation with AXI4-stream video interfaces.
SoC Blockset enables simulation and evaluation of memory transactions in Simulink without the need to deploy a model to an SoC device.
Suggestions for enhancing simulation performance of SoC models.
SoC Blockset enables post-simulation analysis of memory diagnostic data.
Obtain memory interconnect traffic information from a design running on FPGA.