Timing model for transfer of register values
SoC Blockset / Memory
The Register Channel block provides a timing model for the transfer of register values between a processor and hardware logic. The register channel represents the datapath between a processor and a hardware IP via a common configuration bus. Configure the block to include one or more registers, and configure the direction for each register as write if the processor writes to it, or read if the processor reads from it.
Memory Channel | Memory Controller | Memory Traffic Generator