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Getting Started with Targeting Xilinx Versal Adaptive SoC Platform

This example shows how to use HDL Coder™ and the hardware-software co-design workflow to blink LEDs at various frequencies on the Xilinx® Versal® Adaptive SoC platform.

You can use the hardware-software co-design workflow to automate the deployment of your MATLAB® and Simulink® design to a Xilinx Versal Adaptive SoC platform device. You can use this workflow to experiment with ways to partition and deploy your design. This diagram shows the high-level process of generating an IP core and bitstream. For more information, see Targeting FPGA & SoC Hardware Overview.


In this example, you:

  • Set up your Xilinx Versal VCK190 hardware and tools.

  • Generate an HDL IP Core using HDL Workflow Advisor.

  • Integrate the IP core into a Xilinx Vivado project and program the Xilinx Versal hardware.

  • Run FPGA I/O commands to access AXI registers on the FPGA from the MATLAB command prompt.

  • Run a software algorithm in External Mode on the ARM processor from Simulink.


Set Up Xilinx Versal Adaptive SoC Hardware and Tools

1. Set up the Xilinx Versal AI Core Series VCK190 evaluation kit as shown in this image. To learn more about the VCK190 hardware setup, refer to the Xilinx VCK190 board user guide.


2. Connect your computer to the USB JTAG/UART connector of the VCK190 using a USB-C cable.

3. Connect your computer to the top Ethernet connector of the VCK190 using an Ethernet cable.

4. Install the HDL Coder Support Packages for Xilinx FPGA and SoC Devices.

5. Set up the Xilinx Vivado synthesis tool path by entering this command in the MATLAB Command Window. Use your own Vivado installation path.

hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2022.1\bin\vivado.bat');

Generate HDL IP Core Using HDL Workflow Advisor

You can use the HDL Workflow Advisor to automatically generate a shareable and reusable IP core module from a Simulink model. The generated IP core is designed to be connected to an embedded processor on an FPGA device. HDL Coder generates HDL code from the Simulink blocks, and also generates HDL code for the AXI interface logic that connects the IP core to the embedded processor. HDL Coder packages the generated files into an IP core folder. You can then integrate the generated IP core with a larger FPGA embedded design in the Xilinx Vivado environment.

In this example, the subsystem led_counter is the hardware subsystem. It models a counter that blinks the LEDs on an FPGA board. The two input ports, Blink_frequency and Blink_direction, are control ports that determine the LED blink frequency and direction.


Start the IP core generation workflow

1. Open the HDL Workflow Advisor from the led_counter subsystem by right-clicking the led_counter subsystem and choosing HDL Code > HDL Workflow Advisor.

2. In the Set Target > Set Target Device and Synthesis Tool task, set Target workflow to IP Core Generation.

3. Set Target platform to Xilinx Versal AI Core Series VCK190 Evaluation Kit. If you do not have this option, select Get more to open the Support Package Installer. In the Support Package Installer, select Xilinx Versal Platform and follow the instructions to complete the installation.

4. Click Run This Task to run the Set Target Device and Synthesis Tool task.


5 In the Set Target > 1.2. Set Target Reference Design task, set Reference Design to Default system.


6. Click Run This Task to run the Set Target Reference Design task.

Next, configure your design to map to the target hardware by mapping the DUT ports to IP core target hardware and setting DUT-level IP core options. In this example, input ports Blink_frequency and Blink_direction are mapped to the AXI4-Lite interface, so HDL Coder generates AXI interface accessible registers for them. The LED output port is mapped to an external interface, LEDs General Purpose [0:3], which connects to the LED hardware on the Versal board.

1. In the Set Target > 1.3. Set Target Interface task, set the Target Platform Interfaces cell to AXI4-Lite for Blink_frequency, Blink_direction, and Read_back.

2 . Set the Target Platform Interfaces cell to LEDs General Purpose [0:3] for LED.


3. In the Set Target > 1.4. Set Target Frequency task, set Target Frequency to 50.


Next, generate the IP core for your DUT algorithm by right-clicking the Generate RTL Code and IP Core task and selecting Run to Selected Task.


Finally, generate and view the IP core report. After you generate the custom IP core, the IP core files and an HTML custom IP core report are in the ipcore folder in your project folder. The report describes the behavior and contents of the generated custom IP core.


Integrate IP Core with Xilinx Vivado Environment

Next, insert your generated IP core into a embedded system reference design by creating a project, generating an FPGA bitstream, and downloading the bitstream to the Versal hardware.

The reference design is a predefined Xilinx Vivado project. It contains all the elements the Xilinx software needs to deploy your design to the Versal platform, except for the custom IP core and embedded software that you generate.

1. To integrate with the Xilinx Vivado environment, select the Embedded System Integration > 4.1 Create Project task and click Run This Task. A Xilinx Vivado project with an IP Integrator embedded design is generated.


The dialog window includes a link to the project. Optionally, click the link to view the project. From the block diagram in Vivado tool, you can see the HDL Coder generated IP core led_count_ip_0 is connected to the processing system through the AXI interface.


2. Next, select task 4.2 Generate Software Interface.

Enable the Generate host interface script checkbox. The host interface script contains commands that enable you to connect to the target hardware and to write to or read from the generated IP core over the AXI interface. This script will be used below in Run FPGA I/O Commands to Access AXI Registers on FPGA.

Enable Generate Simulink software interface model checkbox. The software interface model contains driver blocks that generate embedded C code and can run on the ARM processor. This model will be used below in Run Software Interface Model in External Mode on ARM Processor.

Click Run This Task.


3. Build the FPGA bitstream in the Build FPGA Bitstream task. Make sure the Run build process externally check box is selected, which runs the Xilinx synthesis tool in a separate process from MATLAB. Wait for the synthesis tool process to finish running


4. After the bitstream is generated, select the 4.4 Program Target Device task. Set Programming method to Download, to program the FPGA bitstream through download mode to the Xilinx Versal VCK190 board. Click Run This Task to program the Versal hardware. HDL Coder copies the generated bitstream to the SD card connected to the Versal hardware.


After you program the FPGA hardware, the LED starts blinking on your Xilinx Versal VCK190 board.


Run FPGA I/O Commands to Access AXI Registers on FPGA

When you select the Generate host interface script option, HDL Coder generates two MATLAB files, gs_hdlcoder_led_blinking_4bit_interface.m and gs_hdlcoder_led_blinking_4bit_setup.m.

  • gs_hdlcoder_led_blinking_4bit_interface.m - This interface script creates a target object, instantiates the setup script and connects to the target hardware. The script sends read and write commands to the generated HDL IP core.

  • gs_hdlcoder_led_blinking_4bit_setup.m - This setup function adds the AXI4 slave interface. The script also contains DUT port objects that have the port name, direction, data type, and interface mapping information. The script maps the DUT ports to the corresponding interfaces.

Follow these steps to access data from the AXI Register by using the readPort and writePort commands:

1. Set up the hardware connection by entering this command in the MATLAB Command Window.

   hProcessor = xilinxsoc

The xilinxsoc function logs in to the hardware over SSH. You can also specify the board's IP address as part of this command.

2. Create a FPGA object by running this command:

   hFPGA = fpga(hProcessor)

3. Run the gs_hdlcoder_led_blinking_4bit_setup(hFPGA) setup function using the generated FPGA object as the input argument. This function configures the FPGA object with the same interfaces as the generated IP core.

4. Run the writePort command to change the blinking frequency of LEDs:

   writePort(hFPGA, "Blink_frequency", 6)

5. Use the readPort command to read the values from the read back port Read_back.

   data_Read_back = readPort(hFPGA, "Read_back")

Run Software Interface Model in External Mode on ARM Processor

When you select the Generate software interface model option, HDL Coder generates a new Simulink model gm_hdlcoder_led_blinking_4bit_interface.slx. This software interface model is used to deploy the software portion of your algorithm. It contains driver blocks which communicate with the algorithm running on the FPGA through the AXI interface. This model generates embedded C code and runs on the ARM processor in the Versal hardware.

When you are prototyping and developing an algorithm, it is useful to monitor and tune the algorithm while it runs on hardware. The External mode feature in Simulink enables this capability. In this mode, the software portion of your algorithm is first deployed to the ARM processor in the Versal hardware, and then linked with the Simulink model on the host computer through an Ethernet connection. Because the ARM processor is connected to the HDL IP core through the AXI interface, you can use External mode to tune parameters, and capture data from the FPGA.


  1. In the generated software interface model, click on the HARDWARE tab in the Simulink toolstrip.

  2. Set Stop Time to inf on the toolstrip.

  3. Click the Monitor & Tune button on the toolstrip to run your model on the ARM processor in External mode. Embedded Coder builds the model, downloads the ARM executable to the Versal hardware, executes it, and connects the model to the executable running on the hardware.

  4. Double-click the Slider Gain block. Change the Slider Gain value and observe the change in frequency of the LED array blinking on the Versal hardware. Double-click the Manual Switch block to switch the direction of the blinking LEDs.

  5. Double-click the scope connected to the Read_back output port and observe that the output data of the FPGA IP core is captured and sent back to the Simulink scope.

  6. When you are done changing model parameters, click the Stop button on the model.



This example shows how the hardware-software co-design workflow helps automate the deployment of your MATLAB and Simulink design to a Xilinx Versal AI Core Series VCK190 Evaluation Kit. You can explore the best ways to partition and deploy your design by iterating through the workflow.

To learn more about the hardware and software co-design workflow, see Hardware-Software Co-Design Workflow for SoC Platforms.