Guided Code Generation
You can generate HDL code for Simulink® models from the UI by using the HDL Code tab in the Simulink toolstrip or by using the Configuration Parameters dialog box. In this dialog box, you can specify various HDL code generation settings including basic folder and language selection to more advanced optimization parameters. To learn about how to generate HDL code from the HDL Code tab, see Generate HDL Code from Simulink Model.
To deploy the generated code to a target device, use the Simulink HDL Workflow Advisor. The Advisor can run end-to-end workflows that check HDL compatibility and deploy the generated code to a target device. HDL Workflow Advisor is not available in Simulink Online™.
Functions
hdladvisor | Display HDL Workflow Advisor |
hdlsetup | Set up model parameters for HDL code generation |
hdlsetuptoolpath | Set up system environment to access FPGA synthesis software |
Checks
Model Settings
HDL Code Generation
Generate HDL for | Select the subsystem or model for HDL code generation |
Language | Specify HDL code generation language |
Code Generation Folder | Specify target folder for generated HDL code |
Restore Model Defaults | |
Run Compatibility Checker | |
Generate |
Target
Workflow | Specify the target workflow |
Project Folder | Folder specification for workflow-specific files (Since R2023b) |
Target Platform | Specify where to deploy generated HDL code (Since R2023b) |
Synthesis Tool | Specify the synthesis tool for targeting the generated HDL code |
Family | Specify target device chip family for the model |
Device | Specify target device name |
Package | Specify target device package name |
Speed | Specify target device speed value |
Reference Design | Configuration parameters to customize reference design (Since R2023b) |
Reference Design Tool Version | Display of reference design tool version (Since R2023b) |
Ignore tool version mismatch | Warning in instances of reference design tool version mismatch (Since R2023b) |
Reference Design Parameters | Parameters available for default reference designs (Since R2023b) |
Target Frequency | Specify target frequency for multiple features and workflows |
Optimization
General
Map pipeline delays to RAM | Map pipeline registers in the generated HDL code to RAM |
RAM mapping threshold | Specify the minimum RAM size for mapping to block RAMs |
Transform non zero initial value delay | Specify Transform Delay blocks to have zero initial value (Since R2020b) |
Remove Unused Ports | Remove unused ports from the design (Since R2020b) |
Enable-based constraints | Meet the timing requirement of the multicycle path in your model |
Pipelining
Allow design delay distribution | Whether to allow distributed pipelining and delay absorption optimizations to move design delays |
Pipeline distribution priority | Priority for the distributed pipelining and delay absorption optimizations |
Clock-rate pipelining | Insert pipeline registers at a clock rate that is faster than the data rate |
Allow clock-rate pipelining of DUT output ports | Produce the DUT outputs as soon as possible by passing the outputs from the DUT at the clock rate rather than the data rate |
Balance clock-rate pipelined DUT output ports | Synchronize the DUT outputs while satisfying the highest-latency requirements of the outputs (Since R2022b) |
Distributed pipelining | Enable pipeline register distribution |
Use synthesis estimates for distributed pipelining | Determine more accurate propagation delays for each component (Since R2022a) |
Adaptive pipelining | Insert pipeline registers to the blocks in your design, reduce the area usage, and maximize the achievable clock frequency on the target FPGA device |
Map lookup tables to RAM | Lookup tables in your design to block RAM and reduce area usage on the target FPGA device (Since R2021b) |
Resource Sharing
Share Adders | Share adders with the resource sharing optimization |
Adder sharing minimum bitwidth | Specify the minimum bit width that is required to share adders with the resource sharing optimization |
Share Multipliers | Share multipliers with the resource sharing optimization |
Multiplier sharing minimum bitwidth | Specify the minimum bit width that is required to share multipliers with the resource sharing optimization |
Multiplier promotion threshold | Share smaller multipliers with other larger multipliers by using the resource sharing optimization |
Multiplier partitioning threshold | Partition multipliers based on a threshold |
Multiply-Add blocks | Share Multiply-Add blocks with the resource sharing optimization (Since R2021a) |
Multiply-Add block sharing minimum bitwidth | Specify the minimum bit width that is required to share Multiply-Add with the resource sharing optimization (Since R2021a) |
Atomic subsystems | Share Atomic Subsystem blocks with the resource sharing optimization |
MATLAB Function blocks | Share MATLAB Function blocks with the resource sharing optimization |
Floating-Point IPs | Share floating-point IPs in the design |
Frame to Sample Conversion
Enable frame to sample conversion | Enable frame-to-sample conversion (Since R2022b) |
Samples per cycle | Specify the size of the signals after the frame-to-sample conversion streams them (Since R2022b) |
Input FIFO size | Specify the register size of the generated input FIFOs around the streaming matrix partitions (Since R2022b) |
Output FIFO size | Specify the register size of the generated output FIFOs around the streaming matrix partitions (Since R2022b) |
Input processing order | Choose between row-major and column-major ordering for the frame inputs (Since R2023a) |
Delay size threshold for external memory (bits) | Specify a threshold size in kilobytes to map large integer delays to input and output DUT ports and offload large delays to external memory outside of your FPGA (Since R2023a) |
Floating Point
Use Floating Point | Specify use of native floating-point library (Since R2023a) |
Latency Strategy | Specify minimum or maximum latency (Since R2020b) |
Handle Denormals | Specify whether to handle denormal numbers (Since R2020b) |
Mantissa Multiplier Strategy | Specify how to implement the mantissa multiplication operation (Since R2020b) |
Vendor Specific Floating Point Library | Select vendor-specific floating-point library (Since R2023a) |
Global Settings
Global Settings
Reset type | Asynchronous or synchronous reset logic for registers |
Reset asserted level | Asserted or active level of the reset input signal |
Clock input port | Name for clock input port |
Clock enable input port | Name for clock enable input port |
Reset input port | Name for reset input port |
Clock inputs | Generation of single or multiple clock inputs |
Treat Simulink rates as actual hardware rates | Oversampling value based on model rates (Since R2023b) |
Clock edge | Active clock edge |
Oversampling factor | Oversampling value |
General
Verilog file extension | File name extension for generated Verilog files |
VHDL file extension | File name extension for generated VHDL files |
SystemVerilog file extension | File name extension for generated SystemVerilog files (Since R2023b) |
Package postfix | Text to append to model or subsystem name |
Entity conflict postfix | Text to resolve duplicate module names |
Split entity file postfix | Text to be appended to model name to form name of generated entity file |
Reserved word postfix | Text to append to value names, postfix values, or labels |
Split arch file postfix | Text to be appended to model name to form name of generated architecture file |
Clocked process postfix | Postfix as character vector |
Split entity and architecture | Number of files entity and architecture code is written to |
Complex real part postfix | Text to append to real part of complex signal names |
VHDL architecture name | Architecture name for DUT |
Complex imaginary part postfix | Text to append to imaginary part of complex signal names |
Module name prefix | Prefix for module or entity name |
Enable prefix | Base name as character vector |
Timing controller postfix | Postfix as character vector |
Pipeline postfix | Text to append to names of input or output pipeline registers |
VHDL library name | Target library name for generated VHDL code |
Generate VHDL or SystemVerilog code for model references into a single library | Code placement for model references |
Block generate label | Postfix to block labels used for HDL GENERATE statements |
Output generate label | Postfix to output assignment block labels |
Instance generate label | Text to append to instance section labels |
Vector prefix | Prefix to vector names |
Instance prefix | Prefix to generated component instance names |
Instance postfix | Postfix to generated component instance names |
Map file postfix | Postfix appended to file name for generated mapping file |
Ports
Input data type | HDL data type for the input ports of the model |
Output data type | HDL data type for the output ports of the model |
Clock Enable output port | Name for the generated clock enable output port |
Minimize clock enables | Minimize clock enable logic |
Minimize global resets | Minimize reset logic |
Use trigger signal as clock | Trigger input signal |
Enable HDL DUT port generation for tunable parameters | Enable creation of DUT input ports for tunable parameters (Since R2021b) |
Balance delays for generated DUT input ports | Insert matching delays on generated DUT inport port paths (Since R2022b) |
Enable HDL DUT port generation for test points | Enable creation of DUT output ports for the test point signals |
Balance delays for generated DUT output ports | Insert matching delays on generated DUT output port paths (Since R2022b) |
Scalarize ports | Vector ports flattened into scalar ports |
Max number of I/O pins for FPGA deployment | Maximum number of I/O pins for target FPGA (Since R2022a) |
Check for DUT pin count exceeding I/O Threshold | Message generated when DUT pin count exceeds maximum number of I/O pins (Since R2023a) |
Coding style
Represent constant values by aggregates | Constants represented by aggregates |
Inline MATLAB Function block code | Inline HDL code for MATLAB Function blocks |
Initialize all RAM blocks | Generate initial signal value for RAM blocks |
RAM Architecture | RAM architecture with or without clock enable |
No-reset registers initialization | Initialize registers without reset and mode of initialization |
Minimize Intermediate Signals | Optimize HDL code for debuggability or code coverage |
Unroll For-Generate Loops | Unroll and omit FOR and GENERATE loops from
generated HDL code |
Generate Parameterized HDL Code from Masked Subsystem | Generate reusable HDL code for subsystems |
Enumerated Type Encoding Scheme | Encoding scheme represent enumeration types |
Use “rising_edge/falling_edge” style for registers | Specify if generated should code use rising_edge function or
falling_edge function |
Code Reuse | Single reusable file to represent the subsystem logic (Since R2022a) |
Inline VHDL configuration | Specify if generated VHDL code includes inline configurations |
Concatenate type safe zeros | Syntax for concatenated zeros in generated VHDL code |
Generate obfuscated HDL code | Specify generation of obfuscated HDL code (Since R2020b) |
Preserve Bus Structure in the Generated HDL Code | Generate code with VHDL record or SystemVerilog structure types (Since R2022b) |
Indexing for Scalarized Port Naming | Starting index for the names of scalarized vector ports (Since R2022a) |
Optimize timing controller | Timing controller entity for speed and code size |
Timing controller architecture | Architecture of generated timing controller |
Use Verilog or SystemVerilog `timescale directives | Use of compiler directives in generated Verilog or SystemVerilog code |
Verilog or SystemVerilog timescale specification | Timescale to use in generated Verilog or SystemVerilog code |
Coding standards
HDL coding standard | Enable the Industry coding standard guidelines |
Show passing rules in coding standard report | Filter the coding standard report so passing rules do not appear (Since R2020b) |
Check for duplicate names | Check for duplicate names in the design (Since R2020b) |
Check for HDL keywords in design names | Check for HDL keywords in design names (Since R2020b) |
Check module, instance, entity name length | Specify whether to check module, instance, and entity name length (Since R2020b) |
Check signal, port, and parameter name length | Specify whether to check signal, port, and parameter name length (Since R2020b) |
Check for clock enable signals | Specify whether to check for clock enable signals in the generated code (Since R2020b) |
Detect usage of reset signals | Specify whether to check for reset signals in the generated code (Since R2020b) |
Detect usage of asynchronous reset signals | Specify whether to check for asynchronous reset signals in the generated code (Since R2020b) |
Minimize use of variables | Specify whether to minimize use of variables (Since R2020b) |
Check for initial statements that set RAM initial values | Specify whether to check for initial statements that set RAM initial values (Since R2020b) |
Check for conditional statements in processes | Specify whether to check for length of conditional statements (Since R2020b) |
Check for assignments to the same variable in multiple cascaded control regions | Specify whether to check if there are assignments to same variable in multiple cascaded control regions (Since R2021b) |
Check if-else statement chain length | Specify whether to check if-else statement chain length (Since R2020b) |
Check if-else statement nesting depth | Specify whether to check if-else statement nesting depth (Since R2020b) |
Check multiplier width | Specify whether to check multiplier bit width (Since R2020b) |
Check for non-integer constants | Specify whether to check for non-integer constants (Since R2020b) |
Check line length | Specify whether to check line lengths in the generated HDL code (Since R2020b) |
Comments
Enable Comments | Enable or disable comments |
Comment in header | Comment lines in header of generated HDL and test bench files |
Emit Time/Date Stamp in Header | Time and date information in the generated HDL file header |
Include Requirements in Block Comments | Generation of requirements comments |
Custom File Header Comment | Custom file header comment |
Custom File Footer Comment | Custom file footer comment |
Model Generation
Generated model | Enable or disable generation of generated model |
Validation model | Enable or disable generation of a validation model |
Suffix for validation model name | Suffix of the validation model name (Since R2020b) |
Prefix for generated model name | Prefix of the generated model name |
Layout Style | Layout style of the generated HDL model (Since R2021b) |
Auto signal routing | Automatic routing of signals in the generated model (Since R2020b) |
Inter-block horizontal scaling | Horizontal scaling of generated model (Since R2020b) |
Inter-block vertical scaling | Vertical scaling of generated model (Since R2020b) |
Advanced
Check for name conflicts in black box interfaces | Specify whether to check for duplicate module or entity names |
Check for presence of reals in generated HDL code | Specify whether to check for reals in the generated HDL code |
Generate HDL code | Enable or disable HDL code generation for model or Subsystem |
Suppress out of bounds access errors by generating simulation-only index checks | Logic that runs during simulation time to prevent array indices from going out of bounds (Since R2022a) |
Report
Generate traceability report | Generate report with hyperlinks from code to model and model to code |
Traceability style | Designation of line-level or comment-based traceability (Since R2020b) |
Generate model Web view | Web view to navigate between code and model |
Generate resource utilization report | Generate report with resource utilization information |
Generate optimization report | Generate report about impacts of HDL Coder optimizations |
Generate high-level timing critical path report | Generate a report that shows estimated critical path in models |
Custom Timing Database Directory | Path to load custom timing (Since R2021b) |
Test Bench
Simulation tool | Simulator for running generated test benches |
HDL code coverage | Enable or disable HDL code coverage flags in generated simulator scripts |
HDL test bench | Enable or disable HDL test bench generation |
Cosimulation model | Enable or disable generation of cosimulation model |
SystemVerilog DPI test bench | Enable or disable SystemVerilog DPI test bench generation |
Test bench name postfix | Specify suffix appended to test bench name |
Force clock | Specify whether the test bench forces clock input signals |
Clock high time (ns) | Specify the period, in nanoseconds, during which the test bench drives clock input signals high (1) |
Clock low time (ns) | Specify the period, in nanoseconds, during which the test bench drives clock input signals low (0) |
Hold time (ns) | Specify a hold time, in nanoseconds, for input signals and forced reset input signals |
Setup time (ns) | Display setup time for data input signals |
Force clock enable | Specify whether the test bench forces clock enable input signals |
Clock enable delay (in clock cycles) | Define elapsed time (in clock cycles) between deassertion of reset and assertion of clock enable |
Force reset | Specify whether the test bench forces reset input signals |
Reset length (in clock cycles) | Define length of time (in clock cycles) during which reset is asserted |
Hold input data between samples | Specify how long subrate signal values are held in valid state |
Initialize test bench inputs | Specify initial value driven on test bench inputs before data is asserted to DUT |
Multi-file test bench | Divide generated test bench into helper functions, data, and HDL test bench code files |
Test bench data file name postfix | Specify suffix added to test bench data file name when generating multi-file test bench |
Test bench reference postfix | Specify character vector to be appended to names of reference signals generated in test bench code |
Use file I/O to read/write test bench data | Create and use data files for reading and writing test bench input and output data |
Ignore output data checking (number of samples) | Specify number of samples during which output data checking is suppressed |
Floating point tolerance check based on | Specify the floating-point tolerance check option |
Tolerance Value | Enter the tolerance value based on the floating-point tolerance check setting that you specify |
Simulation library path | Specify the path to your compiled Altera or Xilinx simulation libraries |
EDA Tool Scripts
Generate EDA scripts | Script files for third-party electronic design automation (EDA) tools |
Compilation Script Parameters
Compile file postfix | Postfix to append to the DUT or test bench name to form the compilation script file name |
Compile initialization | Format name used to write the Init section of the compilation script |
Compile command for VHDL | Format name used to write the Cmd section of the compilation script |
Compile command for Verilog or SystemVerilog | Format name used to write the Cmd section of the compilation script |
Compile termination | Format name used to write the termination portion of the compilation script |
Simulation Script Parameters
Simulation file postfix | Postfix to append to the DUT or test bench name |
Simulation initialization | Format name used to write the initialization section of the simulation script |
Simulation command | Format name used to write the simulation command |
Simulation waveform viewing command | Waveform viewing command written to simulation script |
Simulation termination | Format name used to write the termination portion of the simulation script |
Simulator flags | Simulator flags to apply to generated compilation scripts |
Choose synthesis tool | Generation of synthesis scripts |
Synthesis file postfix | Postfix to append to file name |
Synthesis initialization | Format name used to write initialization section of synthesis script |
Synthesis command | Format name used to write the synthesis command |
Synthesis termination | Format name that is used to write termination portion of synthesis script |
Additional files to add to synthesis project | Additional HDL or constraint files |
Lint Script Parameters
Choose HDL lint tool | Generation of an HDL lint script |
Lint initialization | Initialization text |
Lint command | Command for HDL lint script |
Lint termination | Termination character vector |
Topics
Using HDL Workflow Advisor
- Workflows in HDL Workflow Advisor
Learn about the HDL Workflow Advisor and various workflows you can choose and platforms you can target. - Getting Started with the HDL Workflow Advisor
Learn the basics of the HDL Workflow Advisor and how to run various tasks. - HDL Workflow Advisor Tasks
Describes HDL Workflow Advisor tasks. - Generate Code and Synthesize on FPGA Using HDL Workflow Advisor
The HDL Workflow Advisor guides you through the stages of generating HDL code for a Simulink subsystem and the FPGA design process, such as:
Using Model Configuration Parameters Dialog Box
- Set HDL Code Generation Options
Access HDL options in the Configuration Parameters dialog box, Simulink Toolstrip, or HDL Block Properties window. - Generate HDL Code from Simulink Model Using Configuration Parameters
Use the Configuration Parameters dialog box to generate HDL code for your Simulink model. - Obfuscate Generated HDL Code from Simulink Models
Learn how to obfuscate the generated VHDL®, Verilog® or SystemVerilog code from your model.
Model Configuration Parameters
- Model Configuration Parameters: HDL Code Generation
Use this pane to set code generation parameters, initiate compatibility checking, and generate HDL code for your design. - Model Configuration Parameters: Target
Use this pane to specify the target hardware settings. - Model Configuration Parameters: Optimization
Use this pane to improve area and timing. - Model Configuration Parameters: Floating Point
Use this pane to specify floating-point IP libraries. - Model Configuration Parameters: Global Settings
Use this pane to specify detailed characteristics of the generated code. - Model Configuration Parameters: Report
Use this pane to specify the generation of reports. - Model Configuration Parameters: Test Bench
Use this pane to determine characteristics of generated test bench code. - Model Configuration Parameters: EDA Tool Scripts
Use this pane to control generation of script files for third-party HDL simulation and synthesis tools.
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