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Clock inputs

Generation of single or multiple clock inputs

Model Configuration Pane: Global Settings

Description

Specify generation of single or multiple clock inputs.

Settings

Single (default) | Multiple

Default: Single

Single

Generates a single clock input for the DUT. If the DUT is multirate, the input clock is the primary clock rate, and a timing controller is synthesized to generate additional clocks as required. It is recommended that you use a single clock signal in your design.

Multiple

Generates a unique clock for each Simulink® rate in the DUT. The number of timing controllers generated depends on the contents of the DUT. The oversample factor must be 1 (default) to specify multiple clocks.

For a multirate model, to generate clock for each Simulink rate, make sure to include sequential logic block, such as delay block, at each Simulink rate. If the sequential logic is not present for a particular Simulink rate, HDL Coder™ do not generate the clock signal for that rate.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property while generating HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Use hdlset_param to set the parameter on the model. Then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','ClockInputs','Multiple')
makehdl('sfir_fixed/symmetric_fir')

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir','ClockInputs','Multiple')

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: ClockInputs
Type: character vector
Value: 'Single' | 'Multiple'
Default: 'Single'

Version History

Introduced in R2012a

See Also

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