Simulation tool

Simulator for running generated test benches

Model Configuration Pane: Test Bench

Description

Simulator where you run the generated test benches. The tool generates a script to build and run your HDL code and test bench.

Make sure that the system selected is the DUT. This option is disabled if you select the entire model.

Mentor Graphics ModelSim (default) | Cadence Incisive | Synopsys VCS | Xilinx Vivado Simulator | Custom

Mentor Graphics ModelSim: This option is the default. HDL Coder™ generates the selected types of test benches for use with Mentor Graphics^® ModelSim™.
Cadence Incisive: The code generator generates the selected types of test benches for use with Cadence Incisive^®.
Synopsys VCS: This simulator is supported only for Cosimulation model and SystemVerilog DPI test bench.
Xilinx Vivado Simulator: The code generator generates the selected types of test benches for use with Xilinx^® Vivado^® simulator.
Custom: Selecting this option enables the custom script options on the EDA Tool Scripts pane.

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

No recommendations.

Parameter: SimulationTool (HDL test bench) | GenerateCoSimModel (cosimulation) | GenerateSVDPITestBench | (SystemVerilog DPI test bench)

Type: character vector

SimulationTool Values: 'Mentor Graphics ModelSim' | 'Cadence Incisive' | 'Synopsys VCS' | 'Xilinx Vivado Simulator' | 'Custom'

SimulationTool Default: 'Mentor Graphics ModelSim'

GenerateCoSimModel Values: 'ModelSim' | 'Incisive' | 'VCS' | 'Vivado Simulator' | 'None'

GenerateCoSimModel Default: 'ModelSim'

GenerateSVDPITestBench Values: 'ModelSim' | 'Incisive' | 'VCS' | 'Vivado Simulator' | 'None'

GenerateSVDPITestBench Default: 'ModelSim'

Introduced in R2017a

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