Scalarize ports
Vector ports flattened into scalar ports
Model Configuration Pane: Global Settings / Ports
Description
Flatten vector ports into a structure of scalar ports in VHDL® or SystemVerilog code.
Dependencies
When the target language (specified by the Language option) is VHDL or SystemVerilog, this option is enabled.
Settings
off
(default) | on
| DUT Level
Default: Off
on
When generating code for a vector port, generate a structure of scalar ports.
off
When generating code for a vector port, generate a type definition and port declaration for the vector port.
DUT Level
When generating code for a vector port, generate a structure of scalar ports for vector ports that are at only DUT level. The DUT subsystem does not have to be at the top level of your model.
Tips
To set this property, use the functions hdlset_param
or makehdl
. To view the property value, use
the function hdlget_param
.
When target language (specified by the Language option) is Verilog®, HDL Coder™ flattens the vector signals to scalars by default. In this case, the ScalarizePorts setting will not have any effect.
Recommended Settings
No recommended settings.
Programmatic Use
Parameter: ScalarizePorts |
Type: character vector |
Value: 'on' | 'off' | 'DUT Level' |
Default: 'off' |
Version History
Introduced in R2012b