Model, simulate, and analyze complex systems-on-a-chip (SoCs)
A system-on-a-chip architecture, or SoC architecture, describes a complex integrated circuit that incorporates processor cores, memory, hardware logic, peripherals, and other components, all connected by communications systems such as internal data buses or networks.
You can use MATLAB® and Simulink® to develop algorithms for implementation on SoC architectures, and then analyze how they would perform when partitioned between software running on hard processors. You can then use code generators and hardware support packages to target programmable SoC devices and boards.
Processor cores are the fundamental building blocks in SoC architectures. Many SoCs today are based on processor cores from Arm®, such as the Cortex®-A, Cortex-M, and Cortex-R cores. Other specialized cores used in SoC architectures include Synopsys® ARC® processors, Cadence® Tensilica® Xtensa® processors, and processor cores based on the RISC-V instruction set architecture.
SoC architectures are increasingly based on multiple cores. In symmetric multiprocessing, applications are partitioned across multiple processor cores. In asymmetric multiprocessing, the cores may have distinctly different roles, with some performing hard real-time tasks managing I/O while others perform executive functions. Each of these types of SoC architectures involves challenges in programming and communication.
SoC architectures can incorporate different memory types and configurations. Static random-access memory (SRAM) may be used for processor registers and fast level 1 (or L1) caches, while dynamic random-access memory (DRAM) often makes up the lower-level main memory of SoCs.
For memory-intensive applications such as embedded vision, developers may need off-chip DDR memory to manage the volume of data. The SoC architecture’s memory bandwidth can be an important consideration in the design of these applications. Products like SoC Blockset™ can be used to analyze memory bandwidth for systems modeled in Simulink.
Many peripherals have been incorporated into SoC architectures, often to address popular communications protocols. Popular interfaces include GPIO, PCI-Express, Gigabit Ethernet, CAN, SPI, USB, UART, and I2C.
SoC architectures of microcontrollers include peripherals such as pulse-width modulators (PWM), analog-to-digital converters (ADC), and digital-to-analog converters (DAC). SoC Blockset helps you simulate these peripherals in Simulink during algorithm development, and the SoC Builder app automates the process of configuring the peripherals.
The various modules in SoC architectures must communicate to send instructions and data. Bus-based communication has been used for this purpose since the development of the earliest SoCs. One of the most popular bus architectures is Arm’s Advanced Microcontroller Bus Architecture (AMBA) standard. The AMBA Advanced eXtensible Interface, or AXI, has been widely adopted throughout the semiconductor industry.
In recent years, interconnection networks have emerged as an alternative to bus-based communication in SoC architectures. The interconnection architecture type–often referred to as network-on-a-chip–allows each subsystem to have its own clock domain.
Semiconductor companies including Xilinx®, Intel®, and Microchip have developed programmable SoC architectures as extensions to FPGA product lines. These programmable SoC devices provide users with hardened processor cores along with the programmable logic of conventional FPGAs. Programmable SoCs enable customers to develop hardware/software applications consisting of processor software in combination with libraries of IP cores.
- Xilinx introduced the Zynq®-7000 SoC architecture with an Arm dual-core Cortex-A9 core, and later followed with the Zynq UltraScale+ MPSoC and RFSoC families, which incorporated quad-core Arm Cortex-A53 and dual-core Arm Cortex-R5F processors
- Intel introduced devices with SoC architectures referred to as SoC FPGAs. Cyclone® V SoC, Arria V SoC, and Arria 10 SoC devices are based on Arm dual-core Cortex-A9, whereas the Stratix 10 SoC is based on a quad-core Arm Cortex-A53
- Microchip Technology introduced SmartFusion and SmartFusion2 SoCs based on Arm Cortex-M cores, and more recently, the PolarFire® SoC FPGA family, which incorporates a coherent RISC-V processor cluster
SoC Blockset provides Simulink blocks that you can use to model, simulate, and analyze SoC architectures based on programmable SoCs. SoC Blockset can be used in conjunction with Embedded Coder® to generate readable, compact, and fast C/C++ code for embedded processors, and with HDL Coder™ to generate synthesizable Verilog® and VHDL® code from Simulink models.
Hardware designers generate IP cores within the programmable logic of programmable SoC architectures to accelerate compute-intensive tasks or to produce customized peripherals. You can use HDL Coder to perform custom IP core generation from Simulink models or MATLAB algorithms. In SoC architectures, these IP cores can communicate with tasks running on Arm processors via AXI4 registers or can interface to off-chip devices and signals via external I/O pins.
Examples and How To
See also: SoC Blockset, HDL Coder, Embedded Coder, HDL Verifier, Fixed-Point Designer, Vision HDL Toolbox, FPGA design and SoC codesign, Zynq UltraScale+ RFSoC Design