FPGA, ASIC, and SoC Development

 

MATLAB and Simulink for System Development on Zynq UltraScale+ RFSoC

Use MATLAB® and Simulink® to develop, deploy, and verify wireless systems designs on Xilinx® Zynq® UltraScale+™ RFSoC devices. 

  • Characterize RF performance with data streaming between hardware and MATLAB and Simulink.
  • Leverage standards-compliant (5G and LTE) and custom waveforms.
  • Model and simulate hardware architectures and algorithms.
  • Deploy systems to Zynq Ultrascale+ RFSoC boards using automatic HDL code and C code generation.
  • Debug and verify algorithms running on hardware connected to MATLAB and Simulink test environments.
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Verify System RF Performance with Streaming Data

Use MATLAB and Simulink to stream standards-compliant 5G, LTE, and custom waveforms to and from hardware. Measure results in MATLAB to characterize RF performance for systems such as the Avnet® Zynq UltraScale+ RFSoC Development Kit with Qorvo RF Front End and Avnet Wideband mmWave Radio Development Kit for RFSoC Gen-3.

Xilinx RFSoC and Avnet RFSoC Development Kit

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simulate wireless systems

Simulate Wireless Systems for Xilinx Zynq UltraScale+ RFSoC Devices

Simulate and analyze SoC designs for RFSoC devices. You can partition algorithms between portions to execute on Arm Cortex-53 and IP cores and implement them in programmable logic. You can model the effect communication between processors and programmable logic via AXI4 interconnect as well as communication with off-chip DDR memory.

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RFSOC Boards

Deploy Models to Xilinx Zynq UltraScale+ RFSoC Boards

Configure the RF data converters of RFSoC devices directly from MATLAB. Generate HDL code and embedded C code from algorithm models in Simulink, and deploy systems to prototype hardware like the Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit, Zynq UltraScale+ RFSoC ZCU216 Evaluation Kit, and Zynq UltraScale+ RFSoC ZCU208 Evaluation Kit.

Code Examples and Documentation

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Verify Deployed Algorithms on Zynq UltraScale+ RFSoC Hardware

Rather than writing a Verilog testbench or a VHDL testbench, you can verify your HDL code with MATLAB and Simulink testbenches using HDL cosimulation. Supported simulators include ModelSim™ and Questa™ from Siemens EDA and Cadence® Xcelium®.

Capture signals and upload to MATLAB for analysis

Code Examples and Documentation

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