Design, evaluate, and implement SoC hardware and software architectures
SoC Blockset™ provides Simulink® blocks and visualization tools for modeling, simulating, and analyzing hardware and software architectures for ASICs, FPGAs, and systems on a chip (SoC). You can build your system architecture using memory models, bus models, and I/O models, and simulate the architecture together with the algorithms.
SoC Blockset lets you simulate memory and internal and external connectivity, as well as scheduling and OS effects, using generated test traffic or real I/O data. You can quickly explore different system architectures, estimate interface complexity for hardware and software partitioning, and evaluate software performance and hardware utilization.
SoC Blockset exports reference designs for Xilinx® and Intel® FPGA devices and SoC platforms, including Zynq®-7000, Ultrascale+™, and Intel SoC FPGAs. These reference designs can be used with Xilinx and Intel design tools.
Model and simulate shared memory transactions between hardware logic and embedded processors. Configure DMA memory controllers to arbitrate memory traffic. Account for memory latency and throughput in simulation.
Model task execution in an embedded process as managed by the operating system (OS). Simulate tasks with accurate timing, accounting for context switching, task preemption, and execution duration.
SoC Model Templates
Build complete models of SoC applications from scratch using a step-by-step approach, or start from predefined templates for hardware/software coprocessing, including templates for vision and communication applications.
Simulation with Recorded I/O Data
Record hardware peripheral sources such as RF signals or HDMI data, and then play back recordings as sources in simulations or hardware testing.
Task Execution Analysis
Simulate the software system of SoC applications by running Simulink models that incorporate timer-driven and event-driven tasks. Visualize task execution timing, preemption, rate overruns, drops, and core utilization. Replay task executions in simulation using task timing data captured from previous simulations or directly from SoC devices.
DDR Memory Performance
Analyze the memory bandwidth of system designs. Visualize simulation results and bandwidth metrics before deploying to the SoC device.
On-Device Memory Performance Monitoring and Task Execution Profiling
Measure memory performance and task execution on an SoC device, and then visualize and analyze these measurements to tune an SoC model to meet your system performance requirements. Interact in real time with SoC devices from MATLAB or from your Simulink test bench.
Generate Embedded Software Project
When used with Embedded Coder®, SoC Blockset generates complete embedded software projects from models, including schedulers, software tasks, and I/O device driver integration.
Export Reference Designs
Generate reference designs for programmable logic. Reference designs are configured networks of IP cores with data and control paths that may be connected to external memories and software applications. SoC Blockset connects to Xilinx and Intel design tools to produce bitstreams and then programs FPGA and SoC boards.
Generate Algorithm IP
Generate target-optimized algorithm IP with HDL Coder™. Integrate the generated IP into the reference designs exported from SoC Blockset, and use FPGA vendor tools to produce complete bitstreams.
Generate Application Software
Using Embedded Coder, generate software application code and deploy it to an SoC hardware board. SoC Blockset automatically creates tasks; assigns them to threads; and links interrupts, messages, and system events to the generated code.
Supported Hardware Boards
Implement hardware/software applications on supported hardware kits equipped with Xilinx or Intel FPGAs or SoCs. Target boards using hardware support packages or build support for custom boards.
Testbench Task Block
Model the effect of your external task competing for resources with an application
Proxy Task Block
Model the effect of a task in your application without an explicit task implementation
Hardware Memory Diagnostics
View additional latencies and data overflow information from FPGA execution
Monitor and record execution times of tasks with LTTng
I/O Data Source Block
Read data from a recorded data file at the same time interval at which it was recorded on the hardware board