Vision HDL Toolbox


Vision HDL Toolbox

Design image processing, video, and computer vision systems for FPGAs and ASICs

Reference Applications

Reference applications form a basis for designing, simulating, and deploying computer vision applications on FPGA, ASIC, and SoC devices.

Stereo Camera Semi-Global Block Matching—SGBM

YOLO v2 with Live Camera processing on Zynq

Histogram Equalization for Image Processing—CLAHE

3D LiDAR Segmentation on FPGA

Product Highlights

Use HDL-Optimized Vision Algorithm Blocks

Choose from a range of streaming-pixel based, hardware-optimized library blocks, and system objects to model computationally intensive image and vision processing algorithms. Implement the models on FPGAs, ASICs, and SoCs.

Perform Pixel-Streaming Design

Process 4k and 8k videos and manage input streaming data with built-in pixel control signals, ROI windows, and line buffers. Design and simulate efficient hardware architecture implementations using single or multipixel (2, 4, or 8 pixels per cycle) streaming of vision processing algorithms.

Get Started with Reference Vision Applications

Use and modify pre-built hardware-proven reference sub-systems for resource-efficient implementation of computer vision applications such as automated driving, object detection, and camera pipeline

Model External Memory Interfaces

Use Simulink templates to model external memory interface for AXI and frame buffer to a pixel-streaming design. Model memory accesses from a processor as part of HW/SW codesign and deploy subsystem ports to physical memory interfaces using SoC Blockset capabilities.

Integrate Deep Learning in Vision- Based FPGA Design

Deploy a YOLO v2 deep learning network using pre-built support package reference designs on Zynq-based hardware. Use captured or live camera input for object detection vision applications.

Prototype and Verify on FPGAs and SoCs

Build prototype design with live video input using AMD-Xilinx Zynq Hardware Support Package and model templates. Generate target independent synthesizable VHDL and Verilog code with HDL Coder for supported FPGA or SoC platform. Use HDL Verifier to test and debug your vision hardware designs.

“MATLAB and Simulink cut the time required in the development stage by half. The tools made it easy to respond to our OEM customer’s requirements by enabling the design of custom functions.”

Jiyoung Jeong, LG Electronics

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