Verify VHDL and Verilog using HDL simulators and FPGA-in-the-loop test benches
HDL Verifier™ automatically generates test benches for Verilog® and VHDL® design verification. You can use MATLAB® or Simulink® to directly stimulate your design and then analyze its response using HDL cosimulation or FPGA-in-the-loop with Xilinx®, Intel®, and Microsemi® FPGA boards. This approach eliminates the need to author standalone Verilog or VHDL test benches.
HDL Verifier also generates components that reuse MATLAB and Simulink models natively in simulators from Cadence®, Mentor Graphics®, and Synopsys®. These components can be used as verification checker models or as stimuli in more complex test-bench environments such as those that use the Universal Verification Methodology (UVM).
Verify that HDL code implementation matches MATLAB algorithms and Simulink models.
Debug and Verify System Designs
Use system test benches and golden reference models in MATLAB and Simulink to verify that Verilog or VHDL code meets system specifications. Verify designs using MATLAB or Simulink with Cadence® Incisive® and Xcelium™ simulators, Mentor Graphics® ModelSim® and Questa® simulators, or the Xilinx® Vivado® simulator.
Integrate Existing HDL Code
Incorporate legacy or third-party HDL code into MATLAB algorithms or Simulink models for system-level simulation. Use the Cosimulation Wizard to automatically import Verilog or VHDL code and connect to Mentor Graphics or Cadence HDL simulators.
Measure HDL Code Coverage
Build and evaluate test benches in Simulink by using code coverage analysis tools and interactive source debuggers in Mentor Graphics and Cadence HDL simulators. Perform interactive testing or author scripts to drive batch simulation.
SystemVerilog DPI Generation
Export MATLAB algorithms or Simulink models to ASIC or FPGA verification environments including Synopsys VCS®, Cadence Incisive or Xcelium, and Mentor Graphics ModelSim or Questa.
Generate SystemVerilog DPI components from MATLAB functions or Simulink subsystems as behavioral models for use in functional verification environments.
Generate verification components from MATLAB functions or Simulink models and incorporate them into test benches as scoreboards or sequence items using the Universal Verification Methodology (UVM).
Generate native SystemVerilog assertions from assertions in your Simulink model. Use the generated assertions to ensure consistent validation of design behavior across Simulink and your production verification environment.
Debug and verify algorithms on FPGA boards connected to MATLAB or Simulink test environments.
Use system test benches running in MATLAB or Simulink to test HDL implementations executing on FPGA boards. Connect your host computer automatically to Xilinx, Intel®, and Microsemi® FPGA boards over Ethernet, JTAG, or PCI Express®.
FPGA Data Capture
Capture high-speed signals from designs executing on an FPGA and automatically load them into MATLAB for viewing and analysis. Analyze signals throughout your design to verify expected behavior or investigate anomalies.
Read/Write Memory Access
Access on-board memory locations from MATLAB over JTAG, Ethernet, or PCI Express by inserting an IP core from MathWorks into FPGA designs. Test FPGA algorithms via read or write access to AXI registers and transfer large signal or image files between MATLAB and on-board memory locations.
Integration with HDL Coder
Automate HDL verification tasks by using HDL Verifier with HDL Coder.
FPGA Testing Automation
Perform hardware verification from test benches in MATLAB or Simulink by generating FPGA bitstreams through integration with Xilinx, Intel, and Microsemi development tools. Add test points to Simulink models to capturing signals and loading them into MATLAB for viewing and analysis.
SystemVerilog DPI Test Bench
Generate a SystemVerilog test bench from a Simulink model during HDL code generation. Verify the generated Verilog or VHDL code using the test bench with HDL simulators including Synopsys VCS, Cadence Incisive or Xcelium, Mentor Graphics ModelSim or Questa, and Xilinx Vivado simulators.
Generate IEEE® 1666 SystemC™ TLM 2.0-compatible transaction-level models from Simulink.
Generate SystemC virtual prototype models with TLM 2.0 interfaces for use in virtual platform simulations.
Customize the TLM interfaces of the components you generate by importing IP-XACT™ XML files. Use TLM generator to produce IP-XACT files with mapping information between Simulink and generated TLM components.
FPGA Data Capture Integration with HDL Coder
Specify signals to capture during FPGA testing using test points in Simulink
MATLAB as AXI Master via Ethernet
Perform read and write operations on FPGA boards using MATLAB via Ethernet
MATLAB as AXI Master via PCI Express
Perform high-speed read and write operations on FPGA boards using MATLAB via PCI Express
SystemVerilog Assertion Generation from Simulink Test
Map Test Assessment blocks to assertions in generated DPI components
Generate a SystemVerilog Interface for DPI Components
Choose between a port list or a SystemVerilog interface declaration when generating a SystemVerilog DPI component.
Support For FTDI USB-JTAG Cable
FTDI USB-JTAG connection for MATLAB as AXI Master and FPGA Data Capture.