Test and verify Verilog and VHDL using HDL simulators and FPGA boards
HDL Verifier™ lets you test and verify Verilog® and VHDL® designs for FPGAs, ASICs, and SoCs. You can verify RTL against test benches running in MATLAB® or Simulink® using cosimulation with an HDL simulator. These same test benches can be used with FPGA and SoC development boards to verify HDL implementations in hardware.
HDL Verifier provides tools for debugging and testing FPGA implementations on Xilinx® and Intel® boards. You can use MATLAB to write to and read from memory-mapped registers for testing designs on hardware. You can insert probes into designs and set trigger conditions to upload internal signals into MATLAB for visualization and analysis.
HDL Verifier generates verification models for use in RTL test benches, including Universal Verification Methodology (UVM) test benches. These models run natively in simulators that support the SystemVerilog Direct Programming Interface (DPI).
Debug and Verify System Designs
Use system test benches and golden reference models in MATLAB and Simulink to verify that Verilog or VHDL code meets functional specifications. Verify designs using MATLAB or Simulink with Cadence® Incisive® and Xcelium™ simulators or Mentor Graphics® ModelSim® and Questa® simulators.
Integrate Existing HDL Code
Incorporate legacy or third-party HDL code into MATLAB algorithms or Simulink models for system-level simulation. Use the Cosimulation Wizard to automatically import Verilog or VHDL code and connect to Mentor Graphics or Cadence HDL simulators.
Measure HDL Code Coverage
Evaluate and refine test benches in Simulink using results from code coverage analysis tools and interactive source debuggers in Mentor Graphics and Cadence HDL simulators. Perform interactive testing or author scripts to drive batch simulation.
UVM Component Generation
Generate complete Universal Verification Methodology (UVM) test benches from Simulink models. Generate verification components such as UVM sequences, scoreboards and designs-under-test (DUTs) and incorporate them into production test benches.
SystemVerilog DPI Component Generation
Generate SystemVerilog DPI components from MATLAB functions or Simulink subsystems as behavioral models for use in functional verification environments including Synopsys VCS®, Cadence Incisive or Xcelium, and Mentor Graphics ModelSim or Questa.
Generate native SystemVerilog assertions from assertions in your Simulink model. Use the generated assertions to ensure consistent validation of design behavior across Simulink and your production verification environment.
Use system test benches running in MATLAB or Simulink to test HDL implementations executing on FPGA boards. Connect your host computer automatically to Xilinx, Intel®, and Microsemi® FPGA boards over Ethernet, JTAG, or PCI Express®.
FPGA Data Capture
Capture high-speed signals from designs executing on an FPGA and automatically load them into MATLAB for viewing and analysis. Analyze signals throughout your design to verify expected behavior or investigate anomalies.
Read/Write Memory Access
Access on-board memory locations from MATLAB over JTAG, Ethernet, or PCI Express by inserting an IP core from MathWorks into FPGA designs. Test FPGA algorithms via read or write access to AXI registers and transfer large signal or image files between MATLAB and on-board memory locations.
FPGA Testing Automation
Perform hardware verification from test benches in MATLAB or Simulink by generating FPGA bitstreams through integration with Xilinx, Intel, and Microsemi development tools. Add test points to Simulink models to capture signals and load them into MATLAB for viewing and analysis.
SystemVerilog DPI Test Bench
Generate a SystemVerilog test bench from a Simulink model during HDL code generation. Verify the generated Verilog or VHDL code using the test bench with HDL simulators including Synopsys VCS, Cadence Incisive or Xcelium, Mentor Graphics ModelSim or Questa, and Xilinx Vivado simulators.
Generate SystemC virtual prototype models with TLM 2.0 interfaces for use in virtual platform simulations.
Customize the TLM interfaces of the components you generate by importing IP-XACT™ XML files. Use TLM generator to produce IP-XACT files with mapping information between Simulink and generated TLM components.
Universal Verification Methodology Support
Automatically generate UVM components from Simulink models for use in verification environments
FPGA Data Capture
Capture signals with greater flexibility using comparison operators in defining triggers