Getting Started

Explore mixed-signal systems examples, videos, and tutorials.

These resources provide a path to help engineers ramp up on modeling mixed-signal systems and Model-Based Design (MBD) as quickly and efficiently as possible. The program features a variety of resources including videos, self-paced training, webinars and on-site sessions.

Phase 1 is geared towards people who are new to mixed-signal modeling in Simulink. For users focusing on in-depth modeling of analog systems and impairment, Phase 2 will guide them to learn more about using Simscape. Phase 3 is specifically targeted towards digital design and HDL code generation. Phase 4 covers aspects of verification such as cosimulation and SystemVerilog module generation. Phase 5 provides ongoing support and resources.

To request on-site training, fee-based training or for more information, contact your account manager.

Phase 1: Introduction to Mixed-Signal Modeling

Design and simulate analog and mixed-signal systems such as ADCs and PLLs with Mixed-Signal Blockset.

Video

Design SerDes systems and generate IBIS-AMI models for high-speed interconnects such as DDR, PCI Express, and Ethernet using SerDes Toolbox.

Video

Model and simulate electronic, mechatronic, and electrical power systems using Simscape Electrical.

Video

Generate VHDL and Verilog code for FPGA and ASIC designs using HDL Coder.

Video

In this webinar we demonstrate how engineers can build a coherent design flow for mixed-signal design. We illustrate this through demonstrations and case studies from industry.

Video

Use Mixed-Signal Blockset to model a commercial off-the-shelf integer-N PLL with dual modulus prescaler operating around 4GHz. Verify the PLL performance, including phase noise, lock time, and operating frequency.

Video

Allegro Microsystems explains how they are leveraging MATLAB and Simulink for rapid prototyping, streamlined UVM-based verification, and automatic RTL code generation for mixed signal sensor ICs.

Video

The Mixed-Signal Blockset™ Models provide additional models and examples of typical systems such as PLL, ADC, SerDes, and SMPS highlighting analog/digital integration.

Add-on

This example shows how to design a simple PLL using a reference architecture, and validate the PLL using PLL Testbench.

Documentation

This example shows how to customize a flash ADC by adding the metastability probability as an impairment and how to measure the said impairment.

Documentation

Phase 2: Analog Modeling with Simscape

Design mechatronic systems using Simscape Electrical. An electromechanical actuator and a hybrid electric vehicle show the value of simulation in a design process.

Video

Convert a mechatronic actuator model to C code and simulate in a hardware-in-the-loop configuration. Simscape parameters are tuned on the real-time target.

Video

This example shows how a sigma-delta ADC (analog to digital converter) uses sigma-delta modulation to convert an analog input signal into a digital output signal.

Example

Guidelines for getting started in adopting HDL Coder for your design including examples to illustrate selected concepts.

Example

This one-day course focuses on modeling systems in several physical domains and combine them into a multidomain system in the Simulink® environment using Simscape™.

Fee-based training

Phase 3: Digital Design with HDL Code Generation

Use the data type optimization feature in Fixed-Point Designer to find optimal data types for efficient implementation on an FPGA while meeting constraints on the numerical behavior of your system.

Video

Learn how to take Signal Processing and Communications designs from floating point to efficient fixed point implementation on FPGAs.

Video

This session demonstrates how recent developments in MATLAB and Simulink reduce the cost of developing FPGA and ASIC applications, through strong integration with conventional EDA workflows.

Video

This two-day course shows how to generate and verify HDL code from a Simulink® model using HDL Coder™ and HDL Verifier™.

Fee-based training

This three-day course will review DSP fundamentals from the perspective of implementation within the FPGA fabric.

Fee-based training

Phase 4: Overview of Mixed-Signal Verification

Verify VHDL and Verilog using HDL simulators and FPGA-in-the-loop test benches with HDL Verifier.

Video

Export analog/mixed-signal Simulink models into your SystemVerilog simulator.

Video

Use HDL Verifier to import handwritten or legacy VHDL or Verilog for cosimulation with Simulink.

Video

Guidelines for getting started in adopting HDL Coder for your design including examples to illustrate selected concepts.

Video

PLL simulations are often slow, lengthening project development time. To speed up PLL design, engineers are using MathWorks tools. These tools model feedback efficiently, allow analog and digital components to be simulated together, and have abstract

Video

This example shows how to build a behavioral test bench using SystemVerilog DPI-C component generation.

Example

Phase 5: Ongoing Support

Learn how you can use MATLAB and Simulink products in your workflow at a free seminar in your area.