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UVM Generation

Generate UVM components from Simulink® subsystems or MATLAB® functions

Generate Universal Verification Methodology (UVM) test components and a behavioral design under test (DUT) from a Simulink model. You can use the generated components in two ways.

  • Generate a UVM top model with a test bench and a behavioral (DUT). Use the generated UVM top module as a test environment, and replace the generated behavioral DUT with your own simulation model.

  • Generate UVM test components, and integrate them into your existing UVM environment.

To use this functionality, download and install the ASIC Testbench for HDL Verifier add-on. This feature also requires Simulink Coder™.


uvmbuildGenerate UVM test bench from Simulink model (Since R2019b)


Sequence FeedbackConnect between scoreboard and sequence in UVM test bench model (Since R2023a)


uvmcodegen.uvmconfigUVM configuration object (Since R2020b)
svdpiConfigurationConfigure workflows for UVM and SystemVerilog component generation from MATLAB (Since R2023a)
uvmfTestBenchConfigurationConfigure YAML generation from DPI component generation and its integration with UVMF (Since R2024a)

Model Settings


UVM Generation from Simulink

UVM Generation from MATLAB