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shauk


Active since 2016

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Question


Implement Reset in Simulink
Hallo We have an altrea FPGA, we are generating the design using simulink and then use the hdl coder to generate the vhdl cod...

ongeveer 6 jaar ago | 1 answer | 0

1

answer

Answered
Cascade Filter in HDL Coder
I am using the interpolation filter block from simulink hdl coder library. I have matlab 2014b. I use a serial partition for my ...

meer dan 7 jaar ago | 0

Question


Cascade Filter in HDL Coder
Hallo I am trying to make an interpolation filter of 256 Up sampling. But this is too big for the HDL coder to generate the c...

meer dan 7 jaar ago | 2 answers | 0

2

answers

Question


Convert Block : real world value vs stored integer
in the convert block from simulink, there is a option to chose from *real world value vs stored integer values* which will be eq...

meer dan 7 jaar ago | 1 answer | 0

1

answer

Question


CLK_Enable HDL coder
When generating code in HDL coder. it shows the following line in the clock summary enb_1_4_0 : 2x slower than clk_enable w...

meer dan 7 jaar ago | 1 answer | 0

1

answer

Question


Data Loos in a multi rate system in HDL Coder
Hallo So i am designing a multi rate system in Simulink, that is converted to HDL code using the HDL coder. My design consis...

meer dan 7 jaar ago | 1 answer | 0

1

answer

Answered
HDL Coder Clock Summary Explanation
Hallo Tim Thanks for the answer, solves a lot of confusions. One more question, there is a oversampling parameter in the Simu...

meer dan 7 jaar ago | 0

Question


HDL Coder Clock Summary Explanation
When i am generating a HDL code using the Simulink HDL coder, on the code generation report i get a clock summary report. And th...

meer dan 7 jaar ago | 2 answers | 0

2

answers

Question


Relationship Between Simulink and FPGA Clock
I am designing my model in Simulink and then download it to the FPGA using the HDL coder. My output has a Fs of 11.28 Mhz and my...

meer dan 7 jaar ago | 2 answers | 0

2

answers

Answered
HDL coder Generated Model and Simulink Model Results Does not Match
Hallo thanks for the answer, but could you please explain the line in bit details, or suggest me a documentation where i could...

meer dan 7 jaar ago | 0

Question


HDL coder Generated Model and Simulink Model Results Does not Match
Hallo So i have my model, where 44.1 kHz signal comes in and the output is 11.28 MHz. I am using FIR interpolation filter for...

meer dan 7 jaar ago | 2 answers | 0

2

answers

Question


Feedback Transition to a State in State Flow
<</matlabcentral/answers/uploaded_files/77436/State_Flow.png>> So i want to state 1 the first time with the condition [Rising...

meer dan 7 jaar ago | 1 answer | 0

1

answer

Question


HDL coder Clocking Module
Hallo Can any one explain me how the clocking module works when i am generating HDL code from a simulink model For example l...

meer dan 7 jaar ago | 1 answer | 0

1

answer

Question


HDL Coder Set Target Frequecny
Hallo in the FPGA Turnkey option from HDL coder, there is a option *"1.3 Set Target Frequency"* and it has two sub options *"...

meer dan 7 jaar ago | 1 answer | 0

1

answer

Question


ALTERA DE0-NANO Board Support for HDL Coder
Hallo I have a DE0-NANO development kit ALTERA. I am using MATLAB 2014b and i have a downloaded the ALTERA FPGA board support...

meer dan 7 jaar ago | 1 answer | 0

1

answer

Answered
How can I trigger a transition depending on an input's rise in Stateflow?
Hallo So i am trying to implement the same thing as discussed here. So for the first point about the work around does it mean...

ongeveer 8 jaar ago | 0

Question


Difference between int32 and fixed point
I am trying to program a FPGA using MATLAB and the HDL coder. So for the FPGA i need to have fixed point data types. If i am u...

meer dan 8 jaar ago | 1 answer | 0

1

answer

Question


Does Simulink HDL coder support MEX block?
Hallo Everyone I am looking for a list of blocks supported by the Simulink HDL coder, does the HDL coder support blocks gener...

meer dan 8 jaar ago | 1 answer | 0

1

answer