HDL Coder Clock Summary Explanation
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When i am generating a HDL code using the Simulink HDL coder, on the code generation report i get a clock summary report. And there are two values, Model Based Rate and the DUT Based Rate. I understand where the values come from but i dont understand what they actually mean. So the value in the Model Based Rate is the value I entered in the simulink fundamental sample time and DUT based rate is the maximum Fs of my design. What do they mean and what is the application of this two values, i did not find anything on the documentation
I am attaching a screenshot of my clock summary, As you can see the Left Out and Right Out has a sample time of 8.85771e-08 which is basically 11.28 MHz. Does this ensure that my output data is coming out at 11.28 MHz. This is what i understood by reading the matlab documentation so far.
Tim McBrayer on 30 May 2017
The clock report is primarily intended to show the relationship between the various signal rates. As you have noted, these times are taken directly from Simulink. They are not synthesis results, and there is no guarantee that your HDL code will run at the specified rates once synthesized. The output rates will depend on the master clock fed into the design.
Some people model rates in Simulink using simple integer values instead of desired hardware clock rates. If your design were modeled in such a fashion your output rates might be modeled as 1 (Left_out, Right_out), 4 (WS_OUT), and 256 (sync, msb_bit).