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Feeds
Not possible to set-up SoC Blockset Support Package for AMD FPGA and SoC Devices
Hi Sergei, The setup for the RFSoC for ZCU111 should be straight forward. I see this in R2024b: Select the first option and ...
ongeveer een maand ago | 1
| accepted
ZCU111 FMCP or generic custom port R/W
If the I/O pin is not defined in existing LED, DIP, PB blocks, you can use the ‘I/O Pin’ block to specify the custom pin. open...
10 maanden ago | 0
| accepted
Delay balancing unsuccessful. Cause: Non-discrete rates cannot be handled by delay balancing. Offending block: sqrt_to_hdl
Hi Andrew, You can only generate HDL code from discrete models. That means, you need to set a sample time. Seeing your model yo...
11 maanden ago | 2
| accepted
FIR filter coeff design for FPGA IP core
Hello Nikolaos, If I understand correctly, you are only designing the filter in MATLAB and then use Altera IP directly inste...
ongeveer een jaar ago | 0
| accepted
CP210x USB to UART Bridge VCP Drivers (code 10 in windows device manger)
Hello Ali, I had to install the driver recently to connect the ZCU102 board to a computer with no Vivado Installation (that oft...
ongeveer een jaar ago | 1
| accepted
HDL Coder timing report shows a different negative slack when building the exact model twice
Hi Yeung Pok, I suggest contacting Technical Support to help you with this issue/question. If you go to https://www.mathworks.c...
ongeveer een jaar ago | 0
How to generate IP block from QAM receiver example?
Hi Jakub, First, know that we have toolboxes which come with a streaming interface already (DSP HDL Toolbox, Wireless HDL Toolb...
ongeveer een jaar ago | 0
Error when generating HDL code for deserializer1D
Hi Luca, Maybe by now you did already but I suggest contacting Technical Support to help you with this issue/question. If you g...
ongeveer een jaar ago | 1
Training in programming FPGAs in Matlab/Simulink using examples: from simple to complex
Hi Andrew, First, HDL Coder supports many blocks for generating VHDL, Verilog, and SystemVerilog code. You can find if a block ...
ongeveer een jaar ago | 1
| accepted
Digital Down Converter: # Samples must be Integer multiple of decimation factor
Hi Egor, I agree with Fangjun and suggest contacting Technical Support to help you with this issue/question. If you go to htt...
ongeveer een jaar ago | 0
How to set Unconditional Transition State for Else Statement in HDL Coder with a Counter?
Hello Michael, This is a good catch. Have you tried to use the “after” temporal logic operator on a smaller design? Did the Syn...
ongeveer een jaar ago | 0
| accepted
Is it possible to do an Inference on an Artix7 esp. a Digilent Nexys Video Board?
Hi Silas, I suggest contacting Technical Support to help you with this issue/question. If you go to https://www.mathworks.com...
ongeveer een jaar ago | 1
Good FPGA for learning MATLAB for signal processing and comm
Hello Bogdan, You find information about supported hardware here. There are boards from AMD (Xilinx), Altera (Intel), and Mic...
ongeveer een jaar ago | 1
| accepted
Field-Oriented Control on FPGA SoC and Vivado Design Suite - HLx Editions - 2020.1
Hi Aleksander, in the current version of MATLAB R2023b we support Vivado 2022.1 for this Trenz Motor Control example. If you wa...
ongeveer een jaar ago | 0
Can you use switches as inputs in a design tested with FPGA-in-the-Loop simulation? (on a Zedboard)
Hi Julien, FIL is just for testing an algorithm independently of any peripherals. What you like to do is FPGA Prototyping. S...
ongeveer een jaar ago | 0
| accepted
How to configure Kria KV260 Vision AI Starter Kit for FPGA-in-the-loop with Simulink?
Hi Fabio, I suggest contacting Technical Support to help you with this issue/question. If you go to https://www.mathworks.com/s...
meer dan een jaar ago | 0
HDL Code Generation using remotely installed Vivado
Hi Fabio, this should work on Windows (similar for Linux): hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', ... '\\...
meer dan een jaar ago | 0
| accepted
Deep Learning Network on a Xilinx Cora Z7-10
Hi Martin, You can use Deep Learning HDL Toolbox to deploy a network on FPGAs/SoSs from AMD or Intel. We don't support your boa...
meer dan een jaar ago | 1
Why do I receive the error "Unable to perform assignment because the left and right sides have a different number of elements." in step 3.2 of HDL Workflow Advisor?
Hi Gorka, Have you tried to run the HDL WA with a new project name (Step 1.1)? If this does not help, please share more informa...
meer dan een jaar ago | 0
Simulink/HDLVerifier : error setting property 'status' of class 'CosimWizardPkg.CosimWizardDlg'. Value must contain ASCII characters
Hi Christophe, In the current MATLAB release (R2023b) we only support: Questa® Core/Prime 2022.4 ModelSim® PE 2022.4 ...
meer dan een jaar ago | 0
| accepted
Using a persistent variable array in MATLAB function for HDL Coder
Hi Kaan, it would be good if you could share your MATLAB code you try to implement using the MATLAB Function block. For me it s...
meer dan een jaar ago | 0
Generic data type configuration based on reference precision.
Here the file I used (R2023b).
meer dan een jaar ago | 0
Generic data type configuration based on reference precision.
Hi Eirik, Okay, I think I understand now what you need. First, you only have 27 bits data not 29. Therefore, you want to map th...
meer dan een jaar ago | 0
adi rf som gpio options
Hi Raz, Let me use a shipping example "HW/SW Co-Design QPSK Transmit and Receive Using Analog Devices AD9361/AD9364". I change...
meer dan een jaar ago | 0
| accepted
FPGA Data Capture speed
Hello Jiri, This is quite an ambitious goal. The example "Stream Audio Signal from Intel FPGA Board Using Ready-to-Capture Sign...
meer dan een jaar ago | 0
Using Custom I/Q Sample on "GPS HDL Acquisition and Tracking Using C/A Code" Example
Hi Kaan, it depends on the range of your I/Q samples. In the example the data type is converted from double to fixed-point. Her...
meer dan een jaar ago | 0
FIL I/O options missing in the FIL wizard.
Hi Charanraj, I assume you refer to the FIL I/O panel in the FPGA Board Wizard of the FPGA Board Manager. You can access the FP...
meer dan een jaar ago | 0
How do i define an array as a HDL input?
Starting in R2022a, HDL Coder supports matrix types inputs and outputs at the DUT interface. This enhancement reduces the overhe...
meer dan een jaar ago | 2
| accepted
Implementing Variable Delay Length in Simulink Model for HDL Code Generation
Starting in R2022a, you can generate HDL code for the Variable Integer Delay block. You can now generate code for Delay block th...
meer dan een jaar ago | 0
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