How to generate IP block from QAM receiver example?

I want to generate an IP block from the QAM receiver part from this example:

https://www.mathworks.com/help/comm/ug/hdl-optimized-qam-transmitter-and-receiver.html?searchHighlight=hdl%20qam64&s_tid=srchtitle_support_results_1_hdl%20qam64

To generate an IP core with AXI-stream slave interface using HDL coder it is necessary to specify the valid signal. I do not know what is the right approach to address this.

The model contains a rate transition (there is decimation filter in the Coarse Frequency

Offset Correction ) so it is not possible just wrap the whole system into one enabled subsystem, how it is suggested in this example:

https://www.mathworks.com/help/hdlcoder/ug/model-design-for-axi4-stream-interface-generation.html

How to handle the valid-in signal? Should I split the model to two (or more) enabled submodels before and after the rate transition? Should I manually downsample the valid signal using the downsample block and use the right number of delays to synchronize it?

Is the example just a demonstration of the HDL libraries that nobody intended to use for HDL code generation? What do I miss?

Answer 1

[Tom Richter]

Hi Jakub,

First, know that we have toolboxes which come with a streaming interface already (DSP HDL Toolbox, Wireless HDL Toolbox). With these blocks you would rather model in clock rate than in data rate and even rate conversions are handled by the valid control signals (the model usually is single rate).

Second, you are already on the right track when asking about if you can put everything into an enabled subsystem. Here you find more information on how to Model AXI-Stream Interface.

Third, HDL Coder also supports a Frame-to-Sample Conversion recently. You can model with frames which increases the simulation speed and HDL Coder is then turning the algorithm in a sample based version that again has a streaming interface. Find more about that here.

Best regards,

Tom