HDL Coder timing report shows a different negative slack when building the exact model twice

I'm using HDL coder to deploy a controller model i have onto Speedgoat FPGA. I'm using Vivado as the compiler and the fpga manufacturer is Xilinx. The model has been discretised and converted to fixed-point data types.

The first time i used the HDL workflow advisor to build bitstream from the model i got no negative slack in the timing report (all timing constraints were met), however, a few months later i followed the same process to build the bitstream again from the exact same model, the timing report now says that i've got negative slacks on a few paths, the negative slack time ranges from 0.001ns to 0.056ns.

I was still able to build the bitstream and generate the Simulink Real-Time interface model successfully, despite the presence of negative slack (maybe it's because the negative slack is very small?). I woud like to understand why the two timing reports for the same model show different slack when all i've done was repeat the same process.

Thank you in advance

Answer 1

[Tom Richter]

Hi Yeung Pok,

I suggest contacting Technical Support to help you with this issue/question. If you go to https://www.mathworks.com/support/contact_us.html, you can submit a support request and add example or reproduction files. The page also displays phone contact information based on your location.

The issue you face could have several reasons since you mention some months in between.

• Is it the same MATLAB version and update? -> here HDL Code generation could be different
• Is it the same Vivado version? -> synthesis is different
• Is it the same HDL Coder Integration Package from Speedgoat? -> reference design might be different

We would really like to understand the reason for the difference which can better be discovered with Technical Support.

Best regards,

Tom