How are generics supported in HDL Coder?

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What are the different ways to use GENERIC parameters in HDL Coder?

Accepted Answer

MathWorks Support Team
MathWorks Support Team on 19 Oct 2021
Edited: MathWorks Support Team on 19 Oct 2021
HDL Coder generates parameterized VHDL/Verilog code in the following scenarios:
(1) Use of Model Arguments.
You can use model references and model arguments to generate generic parameters in the generated HDL code for Gain and Constant blocks. The model argument values should resolve to numeric data types at runtime.
(2) Use of Masked Subsystems.
You can generate reusable HDL code for subsystems that have the same tunable mask parameters, but with different values, by enabling 'MaskParameterAsGeneric':
(3) Use of Blackbox Generics.
If you are integrating legacy code using black box subsystem functionality, you can instantiate generic parameters in the module instance using the 'GenericList' parameter:
(4) Use of Address and Data width generics in RAM modules
RAMs are implemented using generic values for address and data widths.
See the attached PDF for an overview.

More Answers (1)

Kiran Kintali
Kiran Kintali on 14 Feb 2018
>> web(fullfile(docroot, 'hdlcoder/ref/maskparameterasgeneric.html'))
Please check this page. You can use mask parameters in Gain, Constant blocks and use MaskParametersAsGeneric feature to generate generic parameters in the generated RTL.
If you are using blackbox subsystem functionality you can instantiate generic parameters in the module instance
web(fullfile(docroot, 'hdlcoder/ug/black-box-implementation-for-subsystem-blocks.html'))
In addition model block parameters and RAM instances can also generate generic parameters during code generation.
Please see attached document for details of these use cases.
  1 Comment
Roman Safronov
Roman Safronov on 18 Feb 2020
Hello Kiran ! Is it possible to generate RTL with parameterized port width (via GENERIC/PARAMETER) ?

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