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Kiran Kintali

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Answered
HDL FIFO accepts three more pushes before signalling full
Can you share the model? thanks

3 dagen ago | 0

| accepted

Answered
How to create or develop an HDL Verifier function for a specific HDL model
https://www.mathworks.com/help/hdlcoder/ug/verify-sobel-edge-detection-algorithm-in-matlab-to-hdl-workflow.html Example that sh...

9 dagen ago | 0

| accepted

Answered
HDL Coder fails to generate VHDL, Assertion failed: b:\matlab\src\cgir_hdl\pir_transforms\corecomplowering.hpp:97
This is an unexpected error. Can you file a bug report with the support team? There should be a readable error message in case ...

9 dagen ago | 0

Answered
HDL Coder Variable Size Matrix
Can you share your design and testbench and the project file used? Thanks

21 dagen ago | 0

Answered
Memory not Initialized in Simulink HDL causing problems in FPGA simulation.
https://www.mathworks.com/help/hdlcoder/ug/rtl-customizations-for-rams.html RTL Customization Parameters for RAMs This page ...

28 dagen ago | 0

Answered
How to update HDL verifier block when VHDL source changes its port definition?
https://www.mathworks.com/help/hdlverifier/ug/import-hdl-code-for-hdl-cosimulation-block.html does your question refer to this ...

28 dagen ago | 0

Answered
How to call vhdl program from matlab script
https://www.mathworks.com/help/hdlcoder/ref/hdl.blackbox-system-object.html Integrate Custom HDL Code Into MATLAB Design h...

ongeveer een maand ago | 0

| accepted

Answered
"Detect Increase" causes multiple identical HDL files to be generated with HDL coder
Please consider this option to increase reuse of shared modules. https://www.mathworks.com/help/hdlcoder/ug/generating-reusab...

ongeveer een maand ago | 0

Answered
Timing error happened when seting series IIR filter in Speedgoat target machine
Please reach out to tech support for guidance on the topic with your model. You can use the workflow to get a high level view o...

ongeveer een maand ago | 0

| accepted

Answered
What are the implications of using the Derivative block in Simulink?
Prachi, You need to use discrete blocks suitable for HDL code generation. See ex: https://www.mathworks.com/help/simulink/slr...

ongeveer een maand ago | 0

Answered
How to convert the simscape sample model('ssc_lithium_cell_1RC') to HDL
The model needs to be made Simscape HDL compliant for FPGA/HIL targeting. Watch out this space for guidance on this topic or rea...

ongeveer een maand ago | 0

Answered
XADC in System Generator/Model Composer for MATLAB
Can you share your Simulink model? Are you trying to utilize HDL Coder workflow advisor IP core generation features? https:/...

ongeveer 2 maanden ago | 0

Answered
converting fixed point simulink model to zynq 706
https://www.mathworks.com/help/supportpkg/xilinxzynqbasedradio/ug/fpga-targeting-workflow.html Communications Toolbox Support P...

2 maanden ago | 0

Answered
Mexw64 file not found in matlab foc example
The example ships mex files only for Windows. You need to have necessary products such as Simscape in place to rebuild mex on ot...

2 maanden ago | 0

| accepted

Answered
Synthesis keeps on running for indefinite time on Xilinx RFSOC ZCU111
Please reach out to support if you still run into this issue.

2 maanden ago | 0

Answered
Can we automatically/directly convert simulink block diagram(simulink model) into MATLAB code ?
https://www.mathworks.com/products/hdl-coder.html HDL Coder supports code generation from both MATLAB and Simulink models. I ...

2 maanden ago | 0

Answered
error in conversion to hdl code"Persistent variable 'y' must be assigned before it is used. The only exception is a check using 'isempty(y)' that can be performed prior to assignment."
You have too much IO on the DUT. (20385 + 200)*dataWordLength ==> too many IO pins. Either you need to stream the inputs an...

2 maanden ago | 0

Answered
how to plot HDL cosimulink output
HDL Verifier Cosimulation Model Generation in HDL Coder https://www.mathworks.com/help/hdlcoder/ug/hdl-verifier-cosimulation-mo...

2 maanden ago | 0

Answered
Convert Matlab Code (.m) to Digital Circuits
Get Started with MATLAB to HDL Workflow https://www.mathworks.com/help/hdlcoder/gs/getting-started-with-matlab-to-hdl-workflo...

2 maanden ago | 1

Answered
Latches inferred from HDL code generated from m-code switch statement
Thank you for the reproduction model. We will try to address the issue if this is still reproducible. Can you share what version...

2 maanden ago | 0

Answered
Use of DSP systems toolbox and computer vision toolbox with HDL coder
You can use this command to view the HDL Comptible Blocks. >> hdllib

2 maanden ago | 0

Answered
HDLcoder ignores coder.const
You can find examples of HDL Coder friendly designs with coder.load and coder.const in the attachment.

2 maanden ago | 0

Answered
MATLAB HDL Coder build error: C compiler produced errors
You can use this helper command to copy any of the HDL Coder friendly MATLAB demo files matlab\toolbox\hdlcoder\hdlcoderdemos\ma...

2 maanden ago | 0

Answered
How do I find the peak of a signal and the time of peak?
Sharing HDL Coder compatible Peak Detector example here. https://www.mathworks.com/matlabcentral/fileexchange/69651-hdl-coder-s...

2 maanden ago | 0

Answered
RAM based circular shift register in Simulink
If you are looking to model delay length via input port using RMA you could use the following style of modeling pattern.

2 maanden ago | 1

Answered
run Simscape HDL Workflow Advisor from script
>> type matlab/toolbox/hdlcoder/hdlcoderdemos/simscapehdldemos/getSSC2HDLSynthesisResults.m This example file shows the workf...

3 maanden ago | 0

Answered
dsp.fft system object unbounded in a for loop
The functions fft() and dsp.fft() do not support HDL streaming interface. You can consider using dsphdl.fft or build a custom F...

3 maanden ago | 0

Answered
Build Standalone application for Zynq 706
There are several product examples that show case how to deploy HDL Coder generated code to target ZC706 board. Check this exam...

3 maanden ago | 1

Answered
Simulink DSP Simulations with Noise: Looking for best practices
You might want to get started with this HDL Coder Evaluation Reference Guide https://www.mathworks.com/matlabcentral/fileexch...

3 maanden ago | 1

Answered
Why do I get the error: " FIL cosimulation failed: the output does not match the expeced result" when I run FPGA-in-the-Loop Test?
If the HDL Code you are running is run with is generated from HDL Coder and is not matching the MATLAB or Simulink testbench the...

3 maanden ago | 0

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