AXI Manager

Access AXI subordinate memory on FPGA board from MATLAB^® or Simulink^®

Note

MATLAB AXI master has been renamed to AXI manager. In the software and documentation, the terms "manager" and "subordinate" replace "master" and "slave," respectively.

Access on-board memory locations from MATLAB or Simulink by using the AXI manager IP in your FPGA design. This IP connects to subordinate memory locations on the board. The IP also responds to read and write commands from MATLAB or Simulink, over JTAG, PCI Express^®, or Ethernet cable.

To use this feature, you must download a hardware support package for your FPGA board. More documentation for this feature is included with the support package installation. See support package documentation:

AXI Manager (HDL Verifier Support Package for Intel FPGA Boards)
AXI Manager (HDL Verifier Support Package for Xilinx FPGA Boards)

For information on downloading support packages, see Download FPGA Board Support Package.

Topics

Overview

Set Up for AXI Manager
High-level steps for accessing memory on an FPGA board from MATLAB or Simulink.

AXI Manager Requirements and Preparation

Download FPGA Board Support Package
The FPGA board support packages contain the definition files for all the supported boards for FPGA-in-the-loop (FIL) simulation, FPGA data capture, or AXI manager.
Set Up FPGA Design Software Tools
Set the MATLAB path to Xilinx^®, Microchip, and Intel^® software.
Guided Hardware Setup
Describes the steps in the automated support package setup process for configuring hardware for use with FPGA-in-the-loop, AXI manager, or FPGA data capture.

Featured Examples

Access FPGA Memory Using JTAG-Based AXI Manager

Use JTAG-based AXI manager to access the memories connected to the FPGA. In the FPGA, there is a Xilinx® DDR memory controller and BRAM controller exist for accessing the DDR memories and the BRAM, respectively. These memory controllers provide an AXI4 subordinate interface for write and read operations by other components in the FPGA. The JTAG-based AXI manager feature provides an AXI manager component that you can use to access any AXI subordinate IPs in the FPGA. This example demonstrates how to integrate AXI Manager IP into a Xilinx Vivado® project and how to write and read data from the DDR memory and the BRAM using MATLAB®. This example simulates the design using the Vivado simulator and then programs the FPGA and performs write and read operations from the MATLAB console.

IP Core Generation Workflow with Ethernet-Based AXI Manager

Uses the HDL Verifier™ Ethernet AXI manager IP to access the HDL Coder™ product generated registers. AXI manager provides access to FPGA registers from MATLAB® directly.