Set Up AXI Manager
MATLAB® AXI master has been renamed to AXI manager. In the software and documentation, the terms "manager" and "subordinate" replace "master" and "slave," respectively.
To access on-board memory locations from MATLAB or Simulink®, you must include the AXI manager IP in your FPGA design. This IP connects to subordinate memory locations on the board. The IP also responds to read and write commands from MATLAB or Simulink, over JTAG, PCI Express® (PCIe), or Ethernet cable.
To use this feature, you must download a hardware support package for your FPGA board. See Download FPGA Board Support Package.
Integrate AXI Manager IP in FPGA Design
To set up the AXI manager IP for access from MATLAB or Simulink, follow these setup steps:
Open Vivado® or Quartus®, and from the IP Catalog select the AXI manager IP in your FPGA design.
When using JTAG as a physical connection, select AXI Manager.
When using Ethernet as a physical connection, select UDP AXI Manager and Ethernet MAC Hub and add them to your project.
When using PCIe as a physical connection, select PCIe AXI Manager and add it to your project.
In your FPGA project, specify which addresses the AXI manager IP is allowed to access.
The AXI manager IP supports AXI4 Lite, AXI4, and Altera® Avalon slave memory locations. The FPGA interconnect automatically converts AXI4 transactions to the protocol of each address.
Compile your FPGA project, including the AXI manager IP.
Connect your FPGA board to your host computer using a physical cable (JTAG, PCIe, or Ethernet cable).
Program the FPGA with your compiled design.
Alternatively, you can perform these steps in the HDL Coder™ guided workflow by using a sample reference design, such as the one included in these examples: Access DUT Registers on Intel Pure FPGA Board Using IP Core Generation Workflow or Access DUT Registers on Xilinx Pure FPGA Board Using IP Core Generation Workflow.
Xilinx® only — Follow these steps when using a JTAG, PCI Express, or programmable logic (PL) Ethernet connection. For a processing system (PS) Ethernet connection, follow the setup steps in Ethernet AXI Manager for Xilinx Zynq SoC Devices. For a USB Ethernet connection, follow the setup steps in USB Ethernet AXI Manager.
After loading the design on your FPGA, you can access memory-mapped locations on the board.
To access the board from MATLAB, create an
aximanager object and use the
to read and write memory-mapped locations on the board.
To access the board from Simulink, create a Simulink model and include AXI Manager Read and AXI Manager Write in it. Configure the blocks to read and write memory-mapped locations on the board. For more information, see Use Simulink to Access FPGA Locations.
When using JTAG as a physical connection to your board, you might have
additional IPs that use the same JTAG connection. Such IPs include FPGA data
capture, Intel® SignalTap II, or Xilinx
Vivado Logic Analyzer cores. The AXI manager IP can coexist in your
design with other IPs that use the JTAG connection, however, only one of these
applications can use the JTAG cable at a time. Release the
aximanager object to return the JTAG resource for use by
However, the nonblocking capture mode enables you to simultaneously use FPGA data capture and AXI manager, which share a common JTAG interface. In this capture mode, you do not need to close or release the JTAG resource to switch between FPGA data capture and AXI manager. For more information, see Simultaneous Use of FPGA Data Capture and AXI Manager.
The most common conflicting use of the JTAG cable is to reprogram the FPGA. Stop any FPGA data capture or AXI manager JTAG connection before you can use the cable to program the FPGA.
The maximum data rate between host computer and FPGA is limited by the JTAG clock frequency. For Intel boards, the JTAG clock frequency is 12 MHz or 24 MHz. For Xilinx boards, the JTAG clock frequency is 33 MHz or 66 MHz. The JTAG frequency depends on the type of cable and the maximum clock frequency supported by the FPGA board.