Coronavirus Disease 2019 (COVID-19) Update

Due to heightened concerns regarding the outbreak of COVID-19, we are adding more instructor-led online training courses as an alternative to classroom courses.

Course Schedule

Prerequisites

Simulink for System and Algorithm Modeling (or Simulink for Automotive System Design or Simulink for Aerospace System Design). Knowledge of C and HDL programming languages.

Programming Xilinx Zynq SoCs with MATLAB and Simulink

This hands-on, two-day course focuses on developing and configuring models in Simulink^® and deploying on Xilinx^® Zynq^®-7000 All Programmable SoCs. The course is designed for Simulink users who intend to generate, validate, and deploy embedded code and HDL code for software/hardware codesign using Embedded Coder^® and HDL Coder^™.

A ZedBoard^™ is provided to each attendee for use throughout the course. The board is programmed during the class and is yours to keep after the training.

Topics include:

Zynq platform overview and environment setup
Introduction to Embedded Coder and HDL Coder
IP core generation and deployment
Using AXI4 interface
Processor-in-the-loop verification
Data interface with real-time application
Integrating device drivers
Custom reference design

Preview the course here.

See detailed course outline

Prerequisites

Simulink for System and Algorithm Modeling (or Simulink for Automotive System Design or Simulink for Aerospace System Design). Knowledge of C and HDL programming languages.

Day 1 of 2
Zynq Platform Overview and Environment Setup	Objective: Configure Zynq-7000 platform and MATLAB environment. Zynq-7000 overview Setting up Zynq platform and software Configuring MATLAB environment Testing connectivity to Zynq hardware
Introduction to Embedded Coder and HDL Coder	Objective: Configure Simulink models for embedded code generation and effectively interpret the generated code. Architecture of an embedded application Generating ERT code Code modules Data structures in generated code Configuring a Simulink model for HDL code generation Using HDL Workflow Advisor
IP Core Generation and Deployment	Objective: Use HDL Workflow Advisor to configure a Simulink model, generate and build both HDL and C code, and deploy to Zynq platform. Configuring a subsystem for programmable logic Configuring the target interface and peripherals Generating the IP core and integrating with SDK Building and deploying the FPGA bitstream Generating and deploying a software interface model Tuning parameters with External Mode
Using AXI4 Interface	Objective: Use various AXI interfaces for data communication between processing system and programmable logic. AXI interface overview AXI4-Lite applications Using AXI4-Stream AXI4 performance considerations
Processor-in-the-Loop Verification	Objective: Use processor-in-the-loop to verify the algorithm running on Zynq platform and profile the execution times in your production algorithm. Processor-in-the-loop (PIL) workflow on Zynq PIL verification with model reference Code execution profiling with PIL PIL considerations

Day 2 of 2
Data Interface with Real-Time Application	Objective: Use the UDP interface to stream data between Simulink and the real-time application running on Zynq platform. Data interface overview Configuring UDP blocks for data streaming Synchronizing data between Simulink and Zynq Data interface with AXI Stream Design partitioning Data interface considerations
Integrating Device Drivers	Objective: Develop device driver interfaces for integrating peripherals on processing system. Workflow for developing device drivers Using the Legacy Code Tool GPIO interface Cross-compiling device drivers
Custom Reference Design	Objective: Create and package reusable IP for Vivado and register custom boards and reference designs. Motivations for a custom reference design Creating reusable IP for Vivado Reference design overview Customizing a reference design Registering board and custom reference design

Guaranteed to Run

When you register for one of these courses, you can rely on the fact that it won't be canceled or rescheduled for any reason.

Course Schedule

Results 1 - 8 of 8

Dates	Location	Language	Price
28 mei 2020- 29 mei 2020	Japan, 東京都	Japanese	JPY 180.000
24 jun 2020- 25 jun 2020	India, Bangalore Register today - only 4 seat(s) remaining	English	INR 42.000
14 sep 2020- 15 sep 2020	US, Ohio, Dayton (Fairborn)	English	USD 1.950
01 okt 2020- 02 okt 2020	France, Paris (Meudon)	English	EUR 1.800
28 okt 2020- 29 okt 2020	Korea (Republic Of), Gangnam, Seoul	Korean	KRW 1.200.000
29 okt 2020- 30 okt 2020	Australia, Sydney (Chatswood)	English	AUD 2.700
10 nov 2020- 11 nov 2020	Germany, Ismaning (bei München)	German	EUR 1.800
07 dec 2020- 08 dec 2020	US, Massachusetts, Natick	English	USD 1.950

Results 1 - 8 of 8

The pricing applies for purchase and use in United States, For pricing in other regions Contact Sales. The product price does not include sales, use, excise, value-added, or other taxes. Any applicable taxes, duties, levies, assessments and governmental charges payable in connection with this purchase will be assessed on the order. Refer to Training Policies for more information