Introduction to 5G NR Signal Detection using Xilinx RFSoC

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This example shows how to deploy a 5G signal detection algorithm to a Xilinx® ZCU111 RFSoC development board, using SoC Blockset™. The example builds on the Introduction to 5G NR Signal Detection (Wireless HDL Toolbox) example, adding the infrastructure and connectivity around the DUT (device under test) to implement the design using hardware. MATLAB® is used to program the hardware, load test data into memory the board, control the deployed design, and to verify the received data.

Signal Detection Algorithm

The signal detection algorithm implemented in this example uses PSS (primary synchronization signal) correlators and thresholding to detect 5G signals, and to determine signal timing information. The SSB (synchronization signal block) containing the detected PSS is OFDM demodulated to recover the SSB grid. The SSB grid contains the PSS, SSS (secondary synchronization signal), and the MIB (master information block). It is 4 OFDM symbols long and 240 subcarriers wide. More information on the signal detection algorithm can be found in the Introduction to 5G NR Signal Detection (Wireless HDL Toolbox) example.

System Architecture

The signal detector, and associated infrastructure, are implemented on the FPGA of the ZCU111. Transmit repeat logic reads a test waveform from DDR memory, and plays back the waveform in a loop, sending the waveform data to the DUT and to the radio transmitter. The DDR memory is accessed from MATLAB to load test waveforms onto the hardware. A switch on the FPGA, controlled from MATLAB, is used to drive the DUT with data from the DDR directly, or data coming from the radio receiver. When used in conjunction with a loopback cable, or transmit and receive antennas, the radio receiver will receive the test data which has been transmitted using the radio transmitter.

Additional sample rate conversion steps are required to convert to and from the sample rates required by the RF data converter (RFDC) interface. A sample rate of 1966.08 MHz is used for the DAC and ADC. The interpolation and decimation modes on the RFDC are used to achieve a sample rate of 245.76 MHz at the interface between the RFDC and the FPGA design. This sample rate, at the interface to the FPGA from the RFDC, is the highest sample rate required on the FPGA so it is also used as the FPGA clock rate. Additional interpolation and decimation filters are implemented on the FPGA to achieve a sample rate of 61.44 MHz. The sample rate 61.44 MHz is used for the test waveform in the DDR memory, and at the interface to the DUT. The signal detecor requires an input sample rate of 7.68 MHz allowing an oversampling factor of 8 compared to the 61.44 MHz rate. This oversampling factor is used to serialize the filters in the signal detector.

The system architecture is implemented in the Simulink® model soc_nrhdlSignalDetection_top.slx. The hardware configuration files are generated from this model using SoC Builder. The RF Data Converter block specifies the parameters of the RF interface. DAC 0 from tile 1, and ADC 0 from tile 1 are used, corresponding to connections J7 and J2 on the XM500 balun card. The DAC and ADC use a sample rate of 1966.08 MSPS. The interpolation and decimation filters in the RF Data Converter are used to change the sample rate by a factor of 8, giving a sample frequency of 245.76 MHz at the stream interface between the RFDC and the FPGA logic. The NCO frequency is set to -1.2 GHz for the DAC and 1.2 GHz for the ADC.

The FPGA design is implemented by the soc_nrhdlSignalDetection_fpga.slx model. The subsystem soc_nrhdlSignalDetection_fpga/SSB Detect and Demod contains the DDR interface logic for waveform transmit repeat and the interpolation and decimation filters required to convert the DUT sample rate of 61.44 MHz to/from the RFDC interface clock rate of 245.76 MHz. The DUT subsystem contains the signal detector and the FIR decimation filter to convert from 61.44 MHz to 7.68 MHz.

Generate Hardware Configuration Files

Use the commands shown to generate the hardware configuration files from the soc_nrhdlSignalDetection_top.slx Simulink model. These commands use the socModelBuilder object to automate the build and deploy steps from the MATLAB command line. This process will take several hours to complete. It will compile the Simulink model, generate HDL code, generate a Vivado project, then run through synthesis, implementation, and bitstream generation.

socBuild = socModelBuilder("soc_nrhdlSignalDetection_top",ProjectFolder="soc_prj",BuildType="FPGA only",ExternalMode=true,RunExternalFPGABuild=false);
socBuild.buildModel;

When the hardware configuration files have been generated you can use the detect5GUsingHardware.mlx live script to deploy the design to the hardware and test the signal detector.

Detect 5G Signals

Use the detect5GUsingHardware.mlx live script to program the FPGA, load test data onto the hardware, then detect 5G signals using the hardware. Before using the detect5GUsingHardware.mlx live script you must have the hardware configuration files available in the soc_proj folder. If you do not have the hardware configuration files, use the instructions in the "Generate Hardware Configuration Files" section to generate the required files.

Program the FPGA by clicking the "Run one time setup" button in the live script. This will connect MATLAB to the board and program the FPGA, as well as setting up the radio interface. The board will be reset as part of this process.

Once the device has been programmed, the detector on the hardware can be used. The code provided in the MATLAB script will generate a test waveform, load the waveform into the DDR memory, then attempt to receive a signal and display the results. On successful detection the received SSB is plotted, and the MIB message will be decoded in MATLAB from the SSB data, allowing verification of the received data.

In the default configuration the DUT is be connected directly to the test data source (sourceSelect drop-down set to "Internal data"). In this configuration the test waveform is read from DDR and passed direct into the DUT. The radio interface is not used.
You can use the subcarrierSpacing dropdown to set the subcarrier spacing of the generated waveform to either 15 or 30 kHz.
You can use the SNR slider to control the amount of noise which is added to the generated waveform. This is specified in dB.
Click the "Run 5G detection on hardware" button in the live script to run the design on the board.

The live script will display information about the operations being performed, and the data received from the hardware. If a PSS is detected two plots of the recovered SSB grid are displayed. The data displayed on each plot is identical, with the second plot labelled to show the locations of the PSS, SSS and PBCH within the grid. If the MIB is successfully decoded from the SSB grid by the MATLAB code the MIB parameters are displayed.

To use the RF loopback configuration, connect a loopback cable between antenna connections J2 and J7 on the board, and change the sourceSelect dropdown to select "RF Loopback". In this configuration the DUT will receive a signal from the radio receiver which, provided a loopback cable has been attached, will be the test data sent via the radio transmitter. Note that the received signal may be attenuated, and contain additional noise compared to using the test data as a direct input to the DUT.

If the SNR is set to a value below 0 dB the detector may fail to detect a signal, or the detector may detect a PSS but the MIB decoding performed in MATLAB may fail.

File Structure

This example uses these files.

Simulink models

soc_nrhdlSignalDetection_top.slx : Represents the top level SoC implementation of the signal detector, connecting the FPGA model, soc_nrhdlSignalDetection_fpga, to the RF Data Converter and AXI interfaces.
soc_nrhdlSignalDetection_fpga.slx : Represents the algorithm deployed to the FPGA. Implements the signal detection algorithm and interface logic.

MATLAB live scripts

detect5GUsingHardware.mlx : Programs the hardware with the generated configuration files, and interacts with the signal detector when it is deployed on the board. Uses the MATLAB files hardwareOneTimeSetup.m and hardware5GSignalDetection.m.

MATLAB code

hardwareOneTimeSetup.m : Used to program the hardware with the generated configuration files. It is called by detect5GUsingHardware.mlx.
hardware5GSignalDetection.m : Runs the signal detector on the hardware. It generates a waveform using the subcarrierSpacing and SNR inputs, writes the waveform to the DDR on the hardware, interacts with the deployed design to run the signal detector, and displays the results. It is called by detect5GUsingHardware.mlx.
setup_soc_model.m : This MATLAB script is used by the soc_nrhdlSignalDetection_top.slx Simulink model to set up the parameters used in the model.
wavegen.m : This MATLAB function generates a basic 5G waveform. It is used by hardware5GSignalDetection.m.
getCorrelationCoeffs.m : This MATLAB function gets the coefficient values for the PSS correlators in the detector.
mibDecode.m : This MATLAB function decodes the MIB information from the SSB grid recovered by the detector.

Further Exploration

This example uses a basic signal detection algorithm which will always demodulate the SSB from the first PSS it encounters with a correlation value that exceeds the threshold. In some cases more control or configuration of the signal detection process may be required, such as demodulating the SSB grid from the strongest PSS detected within an SS Burst. The NR HDL Cell Search (Wireless HDL Toolbox) example implements a more complex signal detection algorithm, reporting all of the detected PSS within a 20ms window along with the PSS correlation strength, timing information and other metrics, allowing for selection of different PSS signals based on user defined criteria.
This example returns the detected SSB grid from the hardware, performing the MIB decoding step in MATLAB. The NR HDL MIB Recovery (Wireless HDL Toolbox) example builds on the NR HDL Cell Search (Wireless HDL Toolbox) example, adding the MIB recovery logic to the FPGA implementation.
This example does not use the embedded processor on the SoC to implement the signal detection or control algorithm. Instead MATLAB is used to decode the MIB and act as the controller. Other examples, such as the 5G NR SIB1 Recovery for FR1 and FR2 Using Xilinx RFSoC Device example, make extensive use of the embedded processor to control the FPGA design, and to implement aspects of the algorithm.