Community Profile

photo

Wang Chen

Last seen: 10 dagen ago Active since 2012

Statistics

  • Knowledgeable Level 3
  • Revival Level 2
  • 3 Month Streak
  • Knowledgeable Level 2
  • First Answer

View badges

Content Feed

View by

Answered
Callback Functions for Custom Reference Design doesn't work
Hi borzack, As you commented, this is likely caused by that MATLAB cannot find my_board.my_ref_design.callback_CustomizeReferen...

3 maanden ago | 0

| accepted

Answered
Error selecting target in R2020a and Vivado 2020
Hi Miquel, For Spartan-6 FPGA device, Xilinx requires Xilinx ISE as synthesis tool. You cannot use Xilinx Vivado for Spartan-6...

8 maanden ago | 0

| accepted

Answered
Running ZYNQ model on different host computer rather than computer on which bit file is generated
Hi Muhammad, This error looks like related to the Embedded Coder build tool chain setup. HDL Workflow Advisor only generate t...

9 maanden ago | 0

Answered
using the HDL workflow advisor for a single registration target which need to include two or more matlab users IP CORES
Hi Raz, It is true that HDL Workflow Advisor currently generates just one User IP core at a time. We are working on removing t...

ongeveer een jaar ago | 0

Answered
How to access AXI-registers of IP-blocks that are already part of custom reference design, not generated with HDLCoder?
Hi Jiarno, HDL Verifier has a MATLAB as AXI Master feature, which you can from MATLAB to control different IPs in your FPGA de...

meer dan een jaar ago | 0

Answered
How do vectorized ports in hdl coder work?
Hi Jay, The expected behaivor is to get [1 2] value for the vector port. This should already be fixed in newer version of t...

meer dan een jaar ago | 0

Answered
Reading Data from PMOD ADC through I2C
Hi Jay, Yes, I2C readback need some extra logic. The HDL Coder example model you mentioned only do I2C write. As Walter menti...

meer dan een jaar ago | 0

Answered
How do I add/register multiple axi interfaces in a zynq reference design?
Hi Hong, HDL Coder generated IP core can only have one AXI4 slave interface. In latest version of MATLAB, HDL Coder will error...

meer dan een jaar ago | 0

Answered
Bad Timing Delays after insterting IP Core generated from Simulink
Hi Alex, It looks like your model does potentially has a long critical path, as I don't see any pipeline delays on the data pa...

ongeveer 2 jaar ago | 0

Answered
HDL Coder - Can it only Generate a project with Vivado 2107.2, not Vivado 2017.4.1
Hi Mike, R2018a version of HDL Coder supports Vivado 2017.2, so please use this version of Vivado. Please see following doc...

meer dan 4 jaar ago | 0

| accepted

Answered
Signal measurement error when using "download"-option in HDL Workflow Advisor
Hi Frederik, When you are using the "Download" programming method, the FPGA bitstream is programmed during the Linux boot up...

meer dan 4 jaar ago | 0

| accepted

Answered
hdl coder led blinking example
Hi Bence, are you using Vivado 2017.4? We noticed that Vivado 2017.4 starts to error out on unconnected AXI Master ports in the ...

meer dan 4 jaar ago | 0

| accepted

Answered
Is it possible to create a custom board for the HDL Coder with the zynq z7100
Hi Patrick, Yes, when using IP core generation workflow in HDL Coder, you can create custom board support for a board with Zynq...

ongeveer 5 jaar ago | 0

| accepted

Answered
How to set up Altera Cyclone V SoC Development Kit for Embedded Coder Support Package?
Hi Netanel, Do you mean the serial connection (USB UART) is timing out? Please set the jumper setting the same as the pic...

bijna 6 jaar ago | 0

Answered
Unable to see AXI Video stream in/out on HDL Advisor for the Sobel filter reference design.
Hi, are you using Xilinx ISE as synthesis tool? In R2016a or earlier version, the "AXI4-Stream Video" interface is only support ...

meer dan 6 jaar ago | 1

| accepted

Answered
How to solve the problem of the file "system_top_wrapper.bit is not found"?
Hi Yahia, This is a bug in HDL Workflow Advisor. Thanks for reporting this! This bug is already fixed in MATLAB version R2...

meer dan 6 jaar ago | 1

Answered
AD9467 HDL Coder adding Custom Reference Design - create_bc_cell issue
The Vivado error message is complaining that it cannot find an IP (analog.com:user:axi_ad9467:1.0) when HDL Workflow Advisor is ...

bijna 7 jaar ago | 0

Answered
How to use the Unit Delay for HDL-Coder on Zedboard Zynq-7000?
Hi Jan, when you run the model on Zynq board, the FPGA part of the design is running at a fast frequency (50MHz). When you are u...

bijna 7 jaar ago | 1

| accepted

Answered
[Coretcl 2-106] Specified part could not be found
Hi Diego, it looks like the Vivado tool you have do not have xc7z045 device support. Are you using Xilinx Vivado Webpack edition...

bijna 7 jaar ago | 0

Answered
HDL Coder - Generate IP Core with Vivado 2015
Hi Zachary, which MATLAB version are you using? If you are using MATLAB and HDL Coder R2015b, the supported Vivado version is Vi...

bijna 7 jaar ago | 0

Answered
HDL WORKFLOW ADVISOR (Errors)
Hi RAJASHEKAR, as the error message sugguested: "Target platform "Xilinx Spartan-6 SP605 development board" requires synthesis...

bijna 7 jaar ago | 1

Answered
Worflow advisor tcl scripts generates error at programming phase
Hi Antti, This is a limitation of current HDL Workflow Advisor (R2015b). There is no option to configure the JTAG programming...

ongeveer 7 jaar ago | 0

| accepted

Answered
what is the difference between FPGA Turnkey and IP Core Generation?
Hi Yashar, Both IP Core Generation and FPGA Turnkey workflows can help you prototype your Simulink/MATLAB algorithm on FPGA/S...

meer dan 7 jaar ago | 10

| accepted

Answered
Generate C code for FPGA
Hi Ran, The recommended workflow is to use HDL Coder to generate HDL Code and IP core for Altera SoC FPGA fabric, and use Emb...

meer dan 7 jaar ago | 1

| accepted

Answered
HDL Coder Workflow Advisor timing analysis
Hi Grégory, You can open Xilinx ISE project from the link generated in HDL Workflow Advisor step 4.1, and change following tw...

bijna 8 jaar ago | 0

| accepted

Answered
Is HDL Coder capable of generating configurable code?
Hi Ethan, GENERIC/PARAM is supported by HDL Coder when you use "Generate parameterized HDL code from masked subsystem" featur...

meer dan 8 jaar ago | 0

| accepted

Answered
Using HDL Coder IP core in Xilinx Vivado instead of EDK
Hi Stefan, Yes, the IP core generation feature for Xilinx Vivado will be supported in MATLAB R2014b release. You can already...

meer dan 8 jaar ago | 0

| accepted

Answered
unable to load valid reference design plugin
Hi Roger, In HDL Workflow Advisor Step 1.2 "Set Target Interface", In the table "Target platform interface table", do you have o...

bijna 9 jaar ago | 0

| accepted

Answered
ZedBoard full Linux for MathWorks HDL Coder
Hi Amir, Ubuntu or any other Linux flavor is not supported by HDL Coder and Embedded Coder support package for Zynq/ZedBoard in...

bijna 9 jaar ago | 0

| accepted

Answered
how could i generate an axi-stream or axi4-lite dma master by hdl coder?
Hi Owen, HDL Coder doesn't support AXI4-Lite Master mode yet. The current AXI4-Lite support is for slave mode only. You can u...

ongeveer 9 jaar ago | 1

Load more