Pulse Generator For HDL conversion!

Hello;

I want to use simulink HDL coder workflow to generate vhdl code for a block that contains a MATLAB function triggered with a pulse generator (as a clock), but when i try to generate, it says that the pulse generator isn't supported for HDL ! so is there any solution or alternative to generate hdl for a triggered matlab function ??

Also if i try to generate the HDL code for the second sub-system (not including pulse generator but MATLAB function only), it gives me the following error:

The top design unit selected for HDL code generation may not be inside a triggered subsystem.

Is there any solution for this problem please?

[Bharath Venkataraman]

Take a look at this MATLAB Answers post to see if it answers your question. You can turn off the global reset and have your own synchronous reset sent in to a delay block - in this case, please use the State Control block set to Synchronous for best HDL behavior.

[Ben Fayçal]

Thank you for the answer sir; i have found a solution to this the problem, but it seems that there are others with the trigger:

-All ports of an enabled/triggered subsystem must have the same sample rate for HDL code generation.

-Subsystem output port 'Out1' must have an initial value of 0 for HDL code generation when in a subsystem with a Trigger, Enable, or Action port.

Is there any solution for that ? or can i make the function work in another way without using a clock and a trigger? which means for example triggering it from the script itself?

[Bharath Venkataraman]

Yes, the requirements for a triggered subsystem are as you mention.

I do wonder if you need the trigger at all. Can you for example, try to model this without a trigger, and rather with enable/valid signals which run the appropriate logic? Here is an example of how to user valid in/out for model the system.

Answer 1

[Kiran Kintali]

>> When i try to generate code, HDL Coder says that the pulse generator isn't supported for HDL !

You can build pulse generator logic using basic blocks such as these and generate HDL Code.