Simulink HDL Coder D-FF With Trigger that isn't clock

Hello, im trying to build a D-FF using HDL Coder in Simulink without a clock trigger signal. The trigger signal I desire is generated outside the subsystem and fed as an input to the subsystem. Whenever I convert the model into HDL, inputs that are not included in the subsystem are added (such as clk, clk_enable). Is there a way to model a DFF with a trigger signal that is not a system clock and translate it into HDL using HDL Coder?

The generated HDL code should be something like this:

------------------------------------------------------------------------------------------------

always @(posedge trigger_signal or negedge rst)

begin

if (!rst)

v_sampled_latched <= pi_ref;

else

v_sampled_latched<=v_sampled_masked;

end

------------------------------------------------------------------------------------------------

I have tried using delay block and triggered subsystem, both add undesired inputs to the system, and use those inputs as trigger to the DFF instead of the signal i desire.

Any help would be greatly appreciated!

Answer 1

[Kiran Kintali]

Thanks for attaching reproduction steps.

I have used trigger as clock feature to see if this addresses your question.

  error_sample u_error_sample (.Trigger(error_sample_1),
                               .reset(reset),
                               .In1(Switch_out1),  // ufix6
                               .vsampled_latch(error_sample_out1)  // ufix6
                               );
                             


`timescale 1 ns / 1 ns

module error_sample
          (Trigger,
           reset,
           In1,
           vsampled_latch);


  input   Trigger;
  input   reset;
  input   [5:0] In1;  // ufix6
  output  [5:0] vsampled_latch;  // ufix6


  reg [5:0] In1_hold;  // ufix6


  always @(posedge Trigger or posedge reset)  // <=== input Trigger signal used as clock signal
    begin : vsampled_latch_hold_process
      if (reset == 1'b1) begin
        In1_hold <= 6'b000000;
      end
      else begin
        In1_hold <= In1;
      end
    end



  assign vsampled_latch = In1_hold;

endmodule  // error_sample

Please check the attached generated code for the model.

>> makehdl('Simulink_PI_Triggered/Discrete Compensator', 'TriggerAsClock', 'on')
### Applying HDL optimizations on the model 'Simulink_PI_Triggered'...
### Begin model generation.
### Model generation complete.
### Begin Verilog Code Generation for 'Simulink_PI_Triggered'.
### Working on Simulink_PI_Triggered/Discrete Compensator/error_sample  as hdlsrc\Simulink_PI_Triggered\error_sample.v.
### Working on Simulink_PI_Triggered/Discrete Compensator/prev_sample1 as hdlsrc\Simulink_PI_Triggered\prev_sample1.v.
### Working on Simulink_PI_Triggered/Discrete Compensator/prev_sample2 as hdlsrc\Simulink_PI_Triggered\prev_sample2.v.
### Working on Simulink_PI_Triggered/Discrete Compensator as hdlsrc\Simulink_PI_Triggered\Discrete_Compensator.v.
### Code Generation for 'Simulink_PI_Triggered' completed.
### Creating HDL Code Generation Check Report Discrete_Compensator_report.html
### HDL check for 'Simulink_PI_Triggered' complete with 0 errors, 1 warnings, and 0 messages.
### HDL code generation complete.

[Itay Israeli]

Thanks for replying Kiran, the code you generated is exactly what I was aiming for.

Although, when trying to generate the code myself by running:

"makehdl('Simulink_PI_Triggered/Discrete Compensator', 'TriggerAsClock', 'on')"

I recieve to following error:

Do you happen to know what might be the problem?

Thanks!

Answer 2

[Kiran Kintali]

The requirement is relaxed in the newer releases.

makehdl('Simulink_PI_Triggered/Discrete Compensator', 'TriggerAsClock', 'on', 'TriggerAsClockWithoutSyncRegisters', 'on')

[Itay Israeli]

Thank you very much, I appreciate the help!

[Itay Israeli]

If I may, I have one last thing to ask. What is to correct way to deal with the "reset" port in the triggered subsystem? Right now, when generating HDL I recieve the following:

----------------------------------------------------------------------------------------------------

always @(posedge Trigger or posedge reset)

begin : vsampled_latch_hold_process

if (reset == 1'b1) begin

In1_hold <= 6'b000000;

end

else begin

In1_hold <= In1;

end

end

----------------------------------------------------------------------------------------------------

And what I would like to have is:

----------------------------------------------------------------------------------------------------

always @(posedge error_sample or negedge rst)

begin

if (!rst)

v_sampled_latched <= pi_ref;

else

v_sampled_latched<=v_sampled_masked;

end

----------------------------------------------------------------------------------------------------

As is shows, the reset port is automatically generated (I don't want the added reset port), and the value set to register In1_hold when reset is set to 0. What I wish to have is a reset port in the triggered subsystem, so I can connect my "rst" port to it, and additionally be able to choose the reset value to an input signal, such as "v_ref". Is that possible?

Much Thanks!

Answer 3

[Kiran Kintali]

you can generate negative edge reset using ResetAssertedLevel option

makehdl(gcb, 'triggerasclock', 'on' , 'ResetAssertedLevel', 'Active-low')

  always @(posedge Trigger or negedge reset)
    begin : vsampled_latch_hold_process
      if (reset == 1'b0) begin
        In1_hold <= 6'b000000;
      end
      else begin
        In1_hold <= In1;
      end
    end

you can remove resets in the generated code using the MinimizeGlobalReset option

makehdl(gcb, 'triggerasclock', 'on', 'minimizeglobalreset', 'on')

  always @(posedge Trigger)
    begin : vsampled_latch_hold_process
      In1_hold <= In1;
    end

[Itay Israeli]

Thank you

Answer 4

[Kiran Kintali]

Can you share a sample model?

[Itay Israeli]

Sure thing

[Itay Israeli]

I have also added an image of the model planned in visio and a verilog code describing the model.

What I aspire to do is generate an HDL Code with HDL Coder that will have the same behavior as the written model, so next time i could use HDL Coder right away without having to write the code.