HDLコード変換した演算ブロックの動作について

HDL Coder（ネイティブ浮動小数モード）でSimulinkモデルをHDLコード生成したとき、

SumやGain等の演算ブロックに相当するコードはクロック（clk）で動作していないと思われます。

しかし、Delayブロックは、clkで動作している様です。

Delayと同様に、演算ブロックをクロックで動作させるためにはどうすれば良いでしょうか。

// <S12>/Gain5
nfp_mul_comp u_nfp_mul_comp_1 (.nfp_in1(kconst_5),  // single
                               .nfp_in2(Delay1_out1),  // single
                               .nfp_out(Gain5_out1)  // single
                               );

// <S12>/Delay
always @(posedge clk or posedge rst_n)
  begin : Delay_process
    if (rst_n == 1'b1) begin
      Delay_out1 <= 32'h0000;
    end
    else begin
      Delay_out1 <= Sum_out1;
    end
  end

Answer 1

[Kiran Kintali]

(Translation)

When HDL code is generated for a Simulink model in HDL Coder (native floating point mode) It seems that the code corresponding to the arithmetic block such as Sum and Gain is not operating on the clock (clk). However, the Delay block seems to be working with clk. How can I make the arithmetic block work with a clock, similar to Delay?

(Response)

For a single rate design HDL Coder native floating point always operates at the same clock rate as the original design. All pipelined delays in the floating point IP use the same clock bundle (clock, enable, reset).

  COMPONENT nfp_mul_single
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          nfp_in1                         :   IN    std_logic_vector(31 DOWNTO 0);  -- single
          nfp_in2                         :   IN    std_logic_vector(31 DOWNTO 0);  -- single
          nfp_out                         :   OUT   std_logic_vector(31 DOWNTO 0)  -- single
          );
  END COMPONENT;

You can also use native floating point operators with zero latency (that is no pipelines added in the floating-point logic) for extremely low latency designs, where no clock bundle used.

  

  COMPONENT nfp_mul_single
    PORT( nfp_in1                         :   IN    std_logic_vector(31 DOWNTO 0);  -- single
          nfp_in2                         :   IN    std_logic_vector(31 DOWNTO 0);  -- single
          nfp_out                         :   OUT   std_logic_vector(31 DOWNTO 0)  -- single
          );
  END COMPONENT;

It is possible you have set the latency strategy for floating-point to ZERO and hence the clock bundle is removed on the floating-point IP instantiation.

See attached zip file with a design with many floating point operators generated with MIN as well ZERO latency and see the changes in the generated code.

To learn more about Latency Strategies (Min, MAX, Zero, Custom) supported by HDLCoder visit the page

https://www.mathworks.com/help/hdlcoder/ug/latency-considerations-with-native-floating-point.html