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CLK_Enable HDL coder

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shauk on 5 Jul 2017
Commented: Jonathan George on 31 Jul 2017
When generating code in HDL coder. it shows the following line in the clock summary
enb_1_4_0 : 2x slower than clk_enable with last phase enb_1_4_1 : 2x slower than clk_enable with phase 1 enb_1_8_1 : 4x slower than clk_enable with phase 1 enb_2_4_0 : 4x slower than clk_enable with last phase
what is the value of the clk_enable here? is it the value of the highest Fs of the sample? my output Fs is 11.2 MHz, which is the highest Fs in the system, or is it the value of the clock that runs the FPGA?

Answers (1)

Tim McBrayer
Tim McBrayer on 5 Jul 2017
I understand your confusion; the wording of this message should more properly refer to 'clk', and not 'clk_enable'.
Your design appears to have three clock rates: the base rate (determined by the master clock), along with rates 2x and 4x slower than the base clock. The slower rates are implemented by feeding each generated FF with the master clock and a clock enable that runs at the appropriate multiple of the base clock. HDL Coder auto-generates a timing controller to drive these enables.
The base rate will be whatever clock you feed to your device. The slower rates in your design will be 2x and 4x slower; controlled by the local clock enables driven by the timing controller.
  1 Comment
Jonathan George
Jonathan George on 31 Jul 2017
I have the same question. Am I supposed to drive the clk signal at some rate equal to or greater than the highest clock rate in the model and then gate it with the clk_enable signal to the model clock rate? (i.e. clk_enable is global enable)
Or does the clk_enable signal some how drive the inputs to the block at one of the lower frequencies?
I haven't seen any documentation that describes clk_enable.

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