Generating higher sampling frequency

I am sampling a sine wave (from hdllib/DSP library) at the rate of 1/1000000 i.e. 1MHz frequency. But my fpga can generate a minimum clock of 5MHz. So, when I tried to increase the sampling frequency in MATLAB to 5MHz it showed an error. Though I made changes in the code generated by HDL Coder, I don't think it's very efficient. Is it possible to have a sampling frequency of 5MHz, or any other tool to work the way around it?

Answer 1

[Kiran Kintali]

Using Oversampling Factor and Latency Strategy

The Oversampling factor (HDL Coder) specifies the factor by which the FPGA clock rate is a multiple of the HDL implementation model base sample rate.

For example if the HDL implementation model contains feedback loops and/or performs complex operations such as multiplication of large matrices that have floating-point data types inside the feedback loops etc., In those situations to accommodate the large latency introduced by these floating-point operations inside the feedback loops, the code generator would require use of oversampling factor in conjunction with the clock-rate pipelining optimization on the model.

For more information, see Strategy 1: Global Oversampling (HDL Coder).

You vary the oversampling factor and latency strategy of the floating-point operator in conjunction.

To achieve the maximum FPGA clock frequency, use the maximum latency strategy. When you specify this latency strategy, the floating-point operations introduce the maximum number of delays. To allocate these delays, increase the oversampling factor. If the increase in FPGA clock frequency outweighs the increase in oversampling factor, you achieve a higher sampling frequency.

To change the latency strategy and oversampling factor in conjunction from the Configuration parameters dialog box:

1. On the HDL Code Generation > Floating Point pane, change the Latency Strategy to Max .
2. On the HDL Code Generation > Global Settings pane, increase the Oversampling factor to a value such as 100 depending on the complexity of your HDL design.