ROM block generated by HDL Coder not inferred by Vivado Synthesis tool

I want to map a LUT in RAM blocks of my FPGA. I followed this example guidelines: http://fr.mathworks.com/help/hdlcoder/examples/getting-started-with-ram-and-rom-in-simulink.html

My synthesis tool is Vivado 2014.2 and my Matlab version is R2015a.

My problem is that the code generated by HDL Coder can not be mapped to RAM by Vivado Synthesis. The generated code by HDL Coder is of this kind:

BEGIN
  In1_unsigned <= unsigned(In1);

    -- <S5>/1-D Lookup Table

    alpha1_D_Lookup_Table_k <= to_unsigned(16#0000#, 14) WHEN In1_unsigned = to_unsigned(16#0000#, 14) ELSE
        to_unsigned(16#3FFF#, 14) WHEN In1_unsigned = to_unsigned(16#3FFF#, 14) ELSE
        In1_unsigned;
    alpha1_D_Lookup_Table_out1 <= nc(to_integer(alpha1_D_Lookup_Table_k));

    -- <S5>/Unit Delay
    Unit_Delay_process : PROCESS (clk)
    BEGIN
      IF clk'EVENT AND clk = '1' THEN
        IF enb = '1' THEN
          Unit_Delay_out1 <= alpha1_D_Lookup_Table_out1;
        END IF;
      END IF;
    END PROCESS Unit_Delay_process;

    Out1 <= std_logic_vector(Unit_Delay_out1);

END rtl;

This generated code can not be mapped to RAM by Vivado but this slightly modified VHDL code can:

BEGIN In1_unsigned <= unsigned(In1);

-- <S5>/1-D Lookup Table

alpha1_D_Lookup_Table_k <= to_unsigned(16#0000#, 14) WHEN In1_unsigned = to_unsigned(16#0000#, 14) ELSE
    to_unsigned(16#3FFF#, 14) WHEN In1_unsigned = to_unsigned(16#3FFF#, 14) ELSE
    In1_unsigned;

-- <S5>/Unit Delay
Unit_Delay_process : PROCESS (clk)
BEGIN
  IF clk'EVENT AND clk = '1' THEN
    IF enb = '1' THEN
      Unit_Delay_out1 <= nc(to_integer(alpha1_D_Lookup_Table_k));
    END IF;
  END IF;
END PROCESS Unit_Delay_process;

Out1 <= std_logic_vector(Unit_Delay_out1);

END rtl;

The only difference is that the output value is extracted from the LUT in the process and not out of it.

So my question is: Is there a way to generate code with the assignment done in a process and not out of it ?

If not, should I consider inserting a System Generator Black Box or something like that in my Simulink design in order to integrate the good VHDL file with the others of my design generated by HDL Coder ?

Answer 1

[Kiran Kintali]

It is possible LUT size in your model does not meet the threshold for ROM mapping on the synthesis tool.

Try the example below.

>> open_system('hdlcoderrom');
>> gcb

ans =

    'hdlcoderrom/ROM'

>> makehdl(gcb)
### Generating HDL for 'hdlcoderrom/ROM'.
### Using the config set for model hdlcoderrom for HDL code generation parameters.
### Running HDL checks on the model 'hdlcoderrom'.
### Begin compilation of the model 'hdlcoderrom'...
### Applying HDL optimizations on the model 'hdlcoderrom'...
### Begin model generation.
### Model generation complete.
### Begin VHDL Code Generation for 'hdlcoderrom'.
### Working on hdlcoderrom/ROM as hdlsrc\hdlcoderrom\ROM.vhd.
### Generating package file hdlsrc\hdlcoderrom\ROM_pkg.vhd.
### Code Generation for 'hdlcoderrom' completed.
### Creating HDL Code Generation Check Report ROM_report.html
### HDL check for 'hdlcoderrom' complete with 0 errors, 1 warnings, and 0 messages.
### HDL code generation complete.