Managing simulink block hierarchy for HDL coder project

I am working on a Simulink project which will be ported to VHDL using HDL coder. For the most part, I am using blocks from Mathworks libraries, but I am also using hierarchy and a few custom function blocks that I have written. I am curious what is the preferred way to manage multiple instances of the same block? Specifically, I wrote a saturating timer function, because the HDL Coder timer did not have quite the behavior I am looking for. This timer shows up multiple times in my Simulink system, but not in a manner where a For Each Subsytem is the right way to capture it.

How should I define custom function blocks and subsytem blocks so that they are only defined once, but instantiated multiple times? My goal is to improve readability of the VHDL output AND to avoid debugging to blocks which are supposed to be identical, but may not be.

Thanks,

Paul

Answer 1

[Amish]

Hi @Paul,

I understand that you are looking for a way to best manage multiple instances of identical custom blocks in Simulink, especially for HDL Coder workflows.

The preferred way, ideally, is to use Library Blocks for reusable components. This can be done by creating a Simulink Library. You can then place your custom function (e.g., your saturating timer subsystem) in a Simulink library (.slx file).

Refer to the following documentation for working with libraries: https://www.mathworks.com/help/simulink/creating-and-using-libraries.html

Once you have this, you can then drag the library block into your main model. Each instance is a linked block to the library definition. This ensures all instances are identical and updates propagate automatically. HDL Coder recognizes library-linked blocks and will generate a single VHDL entity (with multiple instances/components, as appropriate). This improves code readability and avoids code duplication.

As a result, now, each library block becomes a single VHDL entity. Each instance in your model becomes a component instantiation in VHDL as well ass the changes in the library block are reflected in all instances and in the generated VHDL.

Additionally, it is generally a best practice to use Atomic Subsystems. You can make your custom subsystem atomic (set_param(gcb, 'TreatAsAtomicUnit', 'on')). This is required for HDL code generation. You can alos test the library block individually by setting up a 'Testbench'.

Hope this helps!