- You can use the "Generate HDL Code" button in Simulink Toolstrip:
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/1735957/ebaa5c891b3f28a3d4c161fa05976e09.png)
- Or the "Generate HDL for Subsystem" option from the HDL Coder Block context menu:
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/1735962/0d7b711dbe3a912035975b8590407069.png)
- You can also use the "makehdl" command: https://www.mathworks.com/help/hdlcoder/ug/generate-hdl-code-from-simulink-model-from-command-line.html
- Workflow: "Generic ASIC/FPGA"
- Synthesis tool: "No synthesis tool available on system path" or "No synthesis tool specified"
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/1735967/9604dc365d8e1780b7377d49dcc50029.png)
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/1735972/5b6605c8b04a08cdee08c739543dfdda.png)