Model Advisor Checks for DO-254 Standard Compliance
You can check that your model or subsystem complies with selected aspects of the DO-254 safety standard by running the Model Advisor.
To check compliance with DO standards, open the Model Advisor and run the checks in By Task > Modeling Standards for DO-254.
For information on the DO-254 Software Considerations in Airborne Systems and Equipment Certification and related standards, see Radio Technical Commission for Aeronautics (RTCA).
The table below lists the DO-254 checks.
Model Advisor Subfolder | Model Advisor Check | Check ID |
---|---|---|
N/A | Display model version information | mathworks.do178.MdlChecksum |
High-Integrity Systems | See Model Advisor Checks for High-Integrity Systems Modeling Guidelines | |
Library Links | Identify unresolved library links | mathworks.design.UnresolvedLibLinks |
Requirements Consistency | See Model Advisor Checks for Requirements Links | |
HDL Coder | See HDL Code Advisor Checks (HDL Coder) |
Model Checks for High Integrity Systems Modeling
You can check that your model or subsystem complies with selected aspects of the High Integrity System Model safety standard by running the Model Advisor.
To check compliance with High Integrity System Model standards, run the high-integrity checks from By Task > Modeling Standards for DO-254 > High-Integrity Systems
The table below lists the High Integrity System Model checks and their corresponding modeling guidelines that support DO-254 Safety Standard. For more information about the High-Integrity Modeling Guidelines, see High-Integrity System Modeling.
HDL Code Advisor Checks
The HDL Code Advisor and the Model Advisor checks in HDL Coder™ verify and update your Simulink® model or subsystem for compatibility with HDL code generation. The Code Advisor has checks for:
Model configuration settings
Ports and Subsystem settings
Blocks and block settings
Native Floating Point support
Industry standard guidelines
The following table lists the HDL Code Advisor checks that are supported by DO-254 Safety Standards:
HDL Code Advisor Checks | Description |
---|---|
Check for infinite and continuous sample time sources (HDL Coder) | Check source blocks with continuous sample time. |
Check for unsupported blocks (HDL Coder) | Check for unsupported blocks for HDL code generation. |
Check for large matrix operations (HDL Coder) | Check for large matrix operations. |
Identify unconnected lines, input ports, and output ports | Check for unconnected lines or ports. |
Identify disabled library links | Search model for disabled library links. |
Identify unresolved library links | Search the model for unresolved library links, where the specified library block cannot be found. |
Check for MATLAB Function block settings (HDL Coder) | Check HDL compatible settings for MATLAB Function blocks. |
Check for Stateflow chart settings (HDL Coder) | Check HDL compatible settings for Stateflow® Chart blocks. |
Check Delay, Unit Delay and Zero-Order Hold blocks for rate transition | Identify Delay, Unit Delay, or Zero-Order Hold blocks that are used for rate transition. Replace these blocks with actual Rate Transition blocks. |
Check for unsupported storage class for signal objects (HDL Coder) | Check whether signal object storage class is
'ExportedGlobal' or
'ImportedExtern' or
'ImportedExternPointer' |
Check file extension (HDL Coder) | Check file extensions of VHDL files containing entities. |
Check naming conventions (HDL Coder) | Check standard keywords used by EDA tools. |
Check top-level subsystem/port names (HDL Coder) | Check top-level module/entity and port names. |
Check module/entity names (HDL Coder) | Check module/entity names. |
Check signal and port names (HDL Coder) | Check signal and port name lengths. |
Check package file names (HDL Coder) | Check file name containing packages. |
Check generics (HDL Coder) | Check generics at top-level subsystem. |
Check clock, reset, and enable signals (HDL Coder) | Check naming convention for clock, reset, and enable signals. |
Check architecture name (HDL Coder) | Check VHDL architecture name in the generated HDL code. |
Check entity and architecture (HDL Coder) | Check whether the VHDL entity and architecture are described in the same file. |
Check clock settings (HDL Coder) | Check constraints on clock signals. |
Check for global reset setting for Xilinx and Altera devices (HDL Coder) | Check asynchronous reset setting for Altera® devices and synchronous reset setting for Xilinx® devices. |
Check inline configurations setting (HDL Coder) | Check whether you have InlineConfigurations
enabled. |
Check algebraic loops (HDL Coder) | Check model for algebraic loops. |
Check for visualization settings (HDL Coder) | Check model for display settings: port data types and sample time color coding. |
Check delay balancing setting (HDL Coder) | Check Balance Delays is enabled. |
Check for model parameters suited for HDL code generation (HDL Coder) | Check for model parameters set up for HDL code generation. |
Check for double data types in the model (HDL Coder) | Check for double data types in the model. |
Check for Data Type Conversion blocks with incompatible settings (HDL Coder) | Check conversion mode of Data Type Conversion blocks. |
Check for HDL Reciprocal block usage (HDL Coder) | Check HDL Reciprocal blocks are not using floating point types. |
Check for Relational Operator block usage (HDL Coder) | Check Relational Operator blocks which use floating point types have boolean outputs. |
Check for unsupported blocks with Native Floating Point (HDL Coder) | Check for unsupported blocks with native floating-point. |
Check for blocks that have nonzero output latency (HDL Coder) | Check for blocks that have nonzero output latency with native floating-point. |
Check blocks with nonzero ULP error (HDL Coder) | Check for blocks that have nonzero ULP error with native floating-point. |
Check for single datatypes in the model (HDL Coder) | Check for single data types in the model. |
Check for invalid top level subsystem (HDL Coder) | Check for subsystems that cannot be at the top level for HDL code generation. |