Check for root Inports with missing properties
Identifies the following:
root level Inport blocks with missing or inherited sample times, data types or port dimensions for Simulink models.
Using root model Inport blocks that do not have defined sample time, data types or port dimensions can lead to undesired simulation results. Simulink® back-propagates dimensions, sample times, and data types from downstream blocks unless you explicitly assign these values. You can specify Inport block properties with block parameters or Simulink signal objects that explicitly resolve to the connected signal lines.
root level Input ports with missing or inherited data types or port dimensions for Architecture models.
When you run the check, a results table provides links to Inport blocks and signal objects that do not pass, along with conditions triggering the warning.
Available with Simulink Check™.
Results and Recommended Actions
Missing port dimension — Model contains Inport blocks with inherited port dimensions.
|For the listed Inport blocks and Simulink signal objects, specify port dimensions.
Missing signal data type — Model contains Inport blocks with inherited data types.
|For the listed Inport blocks and Simulink signal objects, specify data types.
Missing port sample time — Model contains Inport blocks with inherited sample times.
|For the listed Inport blocks and Simulink signal objects, specify sample times. The sample times for root Inports with bus type must match the sample times specified at the leaf elements of the bus object.
Implicit resolution to a Simulink signal object — Model contains Inport block signal names that implicitly resolve to a Simulink signal object in the base workspace, model workspace, or Simulink data dictionary.
|For the listed Simulink signal objects, in the property dialog, select signal property Signal name must resolve to Simulink signal object. To set this option programmatically, use the port parameter MustResolveToSignalObject.
|One or more Input ports of Architecture model do not have a data interface assigned to it.
|Assign data interfaces to listed Input ports.
Capabilities and Limitations
If the configuration parameter (Configuration Parameters > Solver > Periodic sample time constraint) is set to
Ensure sample time independent, this check does not report warnings when input ports uses inherited sample time.
For export-function models, inherited sample time is not flagged.
Does not run on library models.
Does not support exclusion in Architecture models.
Does not support bus port elements.
Allows exclusions of blocks and charts.