HDL Code Advisor Checks
The HDL Code Advisor and the Model Advisor checks in HDL Coder™ verify and update your Simulink® model or subsystem for compatibility with HDL code generation. The Code Advisor has checks for:
Model configuration settings
Ports and Subsystem settings
Blocks and block settings
Native Floating Point support
Industry standard guidelines
When you run a check, the Code Advisor displays the result as a pass or a failure. You can fix warnings or failures by using the Model Advisor recommended settings.
Model configuration checks
Use the checks in this folder to prepare your model for compatibility with HDL code generation. This folder contains checks that verify whether model parameters are HDL-compatible, whether your design contains algebraic loops, and so on.
|Check for model parameters set up for HDL code generation.|
|Check for global reset setting for Xilinx and Altera devices||Check asynchronous reset setting for Altera® devices and synchronous reset setting for Xilinx® devices.|
|Check inline configurations setting||Check whether you have |
|Check algebraic loops||Check model for algebraic loops.|
|Check for visualization settings||Check model for display settings: port data types and sample time color coding.|
|Check delay balancing setting||Check Balance Delays is enabled.|
Checks for ports and subsystems
This folder contains checks that verify whether ports and subsystems in your model have settings that are compatible for HDL code generation. The checks include whether you have a valid top-level DUT Subsystem and whether you have specified an initial condition for Enabled Subsystem and Triggered Subsystem blocks.
|Check for invalid top level subsystem||Check for subsystems that cannot be at the top level for HDL code generation.|
|Check initial conditions of enabled and triggered subsystems||Check for initial condition of enabled and triggered subsystems.|
Checks for blocks and block settings
These checks verify whether blocks in your model are supported for HDL code generation, and whether the supported blocks have HDL-compatible settings. The checks include whether source blocks in your model have a continuous sample time and whether Stateflow® Charts and MATLAB Function blocks have HDL-compatible settings, and so on.
|Check for infinite and continuous sample time sources||Check source blocks with continuous sample time.|
|Check for unsupported blocks||Check for unsupported blocks for HDL code generation.|
|Check for large matrix operations||Check for large matrix operations.|
|Identify unconnected lines, input ports, and output ports||Check for unconnected lines or ports.|
|Identify disabled library links||Search model for disabled library links.|
|Identify unresolved library links||Search the model for unresolved library links, where the specified library block cannot be found.|
|Check for MATLAB Function block settings||Check HDL compatible settings for MATLAB Function blocks.|
|Check for Stateflow chart settings|
Check HDL compatible settings for Stateflow Chart blocks.
|Check Delay, Unit Delay and Zero-Order Hold blocks for rate transition||Identify Delay, Unit Delay, or Zero-Order Hold blocks that are used for rate transition. Replace these blocks with actual Rate Transition blocks.|
|Check for blocks that have nonzero output latency||Check for blocks that have nonzero output latency with fixed point and native floating point.|
|Check for unsupported storage class for signal objects||Check whether signal object storage class is
|Check for Trigonometric Function block for LUT-based approximation method||Check for Trigonometric Function blocks in a model that use the look up table (LUT) based approximation method.|
|Check for HDL Reciprocal block usage||Check if the model uses HDL Reciprocal blocks.|
If you use the Model Advisor, you see the Identify unconnected lines, input ports, and output ports, Identify disabled library links, Identify unresolved library links, and Check Delay, Unit Delay and Zero-Order Hold blocks for rate transition in the Simulink folder.
Native Floating Point checks
These checks verify whether the model is compatible for HDL code generation in
Native Floating Point mode. The checks include whether the
blocks in your Simulink model are supported for HDL code generation with
Floating Point, and whether the model uses single data types, and so
on. Native floating-point support in HDL Coder generates target-independent HDL code from your single-precision
floating-point model. For more information, see Generate Target-Independent HDL Code with Native Floating-Point.
|Check for single datatypes in the model||Check for |
|Check for double datatypes in the model with Native Floating Point||Check for |
|Check for Data Type Conversion blocks with incompatible settings||Check conversion mode of Data Type Conversion blocks.|
|Check for HDL Reciprocal block usage||Check HDL Reciprocal blocks are not using floating point types.|
|Check for Relational Operator block usage||Check Relational Operator blocks which use floating point types have boolean outputs.|
|Check for unsupported blocks with Native Floating Point||Check for unsupported blocks with native floating-point.|
|Check blocks with nonzero ulp error||Check for blocks that have nonzero ulp error with native floating-point.|
industry standard checks
These checks verify whether your Simulink model conforms to the industry-standard rules. industry-standard rules recommend using certain HDL coding guidelines. When generating code, HDL Coder displays an HDL coding standard report that shows how well the generated code adheres to the industry-standard guidelines.
|Check file extension||Check file extensions of VHDL files containing entities.|
|Check naming conventions||Check standard keywords used by EDA tools.|
|Check top-level subsystem/port names||Check top-level module/entity and port names.|
|Check module/entity names||Check module/entity names.|
|Check signal and port names||Check signal and port name lengths.|
|Check package file names||Check file name containing packages.|
|Check generics||Check generics at top-level subsystem.|
|Check clock, reset, and enable signals||Check naming convention for clock, reset, and enable signals.|
|Check architecture name||Check VHDL architecture name in the generated HDL code.|
|Check entity and architecture||Check whether the VHDL entity and architecture are described in the same file.|
|Check clock settings||Check constraints on clock signals.|
For more information, see: