Check for root Outports with missing properties
Identifies the following:
root level Outport blocks with missing or inherited sample times, data types or port dimensions for Simulink models.
Using root model Outport blocks that do not have defined sample time, data types or port dimensions can lead to undesired simulation results. Simulink® back-propagates dimensions, sample times, and data types from downstream blocks unless you explicitly assign these values. You can specify outport block properties with block parameters or Simulink signal objects that explicitly resolve to the connected signal lines.
root level Output ports with missing or inherited data types or port dimensions for Architecture models.
When you run the check, a results table provides links to Outport blocks and signal objects that do not pass, along with conditions triggering the warning.
Available with Simulink Check™.
Results and Recommended Actions
Missing port dimension — Model contains Outport blocks with inherited port dimensions.
|For the listed Outport blocks and Simulink signal objects, specify port dimensions.
Missing signal data type — Model contains Outport blocks with inherited data types.
|For the listed Outport blocks and Simulink signal objects, specify data types.
Missing port sample time — Model contains Outport blocks with inherited sample times.
|For the listed Outport blocks and Simulink signal objects, specify sample times. The sample times for root Outports with bus type must match the sample times specified at the leaf elements of the bus object.
Implicit resolution to a Simulink signal object — Model contains Outport block signal names that implicitly resolve to a Simulink signal object in the base workspace, model workspace, or Simulink data dictionary.
|For the listed Simulink signal objects, in the property dialog, select signal property Signal name must resolve to Simulink signal object. To set this option programmatically, use the port parameter MustResolveToSignalObject.
|One or more Output ports of Architecture model do not have a data interface assigned to it.
|Assign data interfaces to listed Output ports.
Capabilities and Limitations
Allows exclusions of blocks and charts.
Does not support exclusion in Architecture models.