Creating an FPGA-in-the-loop link between the simulator and the board enables you to:
Verify HDL implementations directly against algorithms in Simulink® or MATLAB®.
Apply data and test scenarios from Simulink or MATLAB to the HDL design on the FPGA.
Integrate existing HDL code with models under development in Simulink or MATLAB.
Before you can use FPGA-in-the-loop (FIL) simulation, you must download the support package for your board. See Download FPGA Board Support Package. Alternatively, you can manually create custom board definition files for use with FIL simulation. See FPGA Board Customization.
|FPGA-in-the-Loop Wizard||Generate an FPGA-in-the-loop (FIL) block or System object from existing HDL files|
|FIL simulation with MATLAB|
|Load programming file onto FPGA|
|FIL Simulation||Simulate HDL code on FPGA hardware from Simulink|
Choose between generating a block or System object™, and decide whether to use the FIL Wizard or HDL Workflow Advisor.
FPGA-in-the-loop (FIL) simulation provides the capability to use Simulink or MATLAB software for testing designs in real hardware for any existing HDL code.
FIL Requirements and Preparation
DUT guidelines for FIL simulation of blocks and System objects.
The FPGA board support packages contain the definition files for all the supported boards for FPGA-in-the-loop (FIL) simulation, data capture, or MATLAB AXI master.
Set the MATLAB path to Xilinx®, Microsemi®, and Intel® software.
Describes the steps in the automated support package setup process for configuring hardware for use with FPGA-in-the-loop.
Describes the steps necessary to prep hardware and hardware tools for FIL.
Generate FIL Interface from Legacy Code
Generate a FPGA-in-the-Loop block from existing HDL source files, then include the FPGA implementation in a Simulink simulation.
Generate a FPGA-in-the-Loop System object from existing HDL source files, then include the FPGA implementation in a MATLAB simulation.
This example shows you how to set up an FPGA-in-the-Loop (FIL) application using HDL Verifier™.
This example shows you how to verify a digital up-converter design generated with Filter Design HDL Coder™ using FPGA-in-the-Loop simulation.
Generate FIL System Object from MATLAB Code (requires HDL Coder license)
Generate an FPGA-in-the-loop System object and test bench using HDL Workflow Advisor.
Generate FIL Block from Simulink Model (requires HDL Coder license)
Generate test bench and code coverage for generated HDL code using the HDL Workflow Advisor.
Generate an FPGA-in-the-loop model using HDL Workflow Advisor.
Fixes for common error messages and issues.