Generate HDL verification artifacts and follow verification workflows from a Simulink subsystem
The HDL Verifier app enables you to generate a SystemVerilog DPI component, an HDL Cosimulation block, or an FPGA-in-the-loop block from a Simulink® subsystem. The app then guides you through the workflow required to verify your HDL.
Select the HDL Verifier™ workflow on the left pane, under HDL Verifier Mode:
HDL Cosimulation — Select this option to generate an HDL Cosimulation block. Follow the toolstrip sections to prepare and run an HDL cosimulation, and then view the results.
DPI Component Generation — Select this option to generate a SystemVerilog DPI component. Follow the toolstrip sections to prepare and generate the component, and then view the results.
FPGA-in-the-Loop (FIL) — Select this option to generate an FIL Simulation block. Follow the toolstrip sections to load the design to your FPGA board, prepare and run a FIL simulation, and review the results.
Open the HDL Verifier App
Simulink Toolstrip: On the Apps tab, under Code verification, validation, and test, click HDL Verifier. The HDL Verifier app opens in its own tab on the Simulink Toolstrip.
Version HistoryIntroduced in R2020b
R2023b: DPI component generation requires ASIC Testbench
To access DPI and UVM component generation features, you must download the ASIC Testbench for HDL Verifier add-on.
R2023b: Simulink Toolstrip support for FPGA-in-the-loop workflow
To access FPGA-in-the-loop with Simulink, open the HDL Verifier app and select FPGA-in-the-Loop on the HDL Verifier Mode pane.
R2021a: Simulink Toolstrip support for HDL cosimulation workflow
To access HDL cosimulation with Simulink, open the HDL Verifier app and select HDL Cosimulation on the HDL Verifier Mode pane.