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Model Design for AXI4-Stream Interface Generation

With the HDL Coder™ software, you can implement a simplified, streaming protocol in your model. The software generates AXI4-Stream interfaces in the IP core.

Simplified Streaming Protocol

To map the design under test (DUT) ports to AXI4-Stream interfaces, use the simplified AXI4-Stream protocol. You do not have to model the actual AXI4-Stream protocol and instead you can use the simplified protocol. When you run the IP Core Generation workflow, the generated HDL code contains wrapper logic that translates between the simplified protocol and the actual AXI4-Stream protocol. The simplified protocol requires fewer protocol signals, eases the handshaking mechanism between valid and ready signals, and supports bursts of arbitrary lengths.

Use the simplified AXI4-Stream protocol for write and read transactions. When you want to generate an AXI4-Stream interface in your IP core, in your DUT interface, implement the following signals:

  • Data

  • Valid

Optionally, when you map scalar DUT ports to an AXI4-Stream interface, you can model the following signals:

  • Ready

  • Other protocol signals, such as:

    • TSRTB

    • TKEEP

    • TLAST

    • TID

    • TDEST

    • TUSER

Data and Valid Signals

When the Data signal is valid, the Valid signal is asserted. This diagram illustrates the Data and Valid signal relationship according to the simplified streaming protocol. When you run the IP core generation workflow, HDL Coder adds a streaming interface module in the HDL IP core that translates the simplified protocol to the full AXI4-stream protocol. In this diagram the clock signal is represented by clk.

Sample-Based Modeling

When you want to simulate the data signal as a stream of samples on the DUT boundary, model in sample-based mode. In sample-based mode you can model the data signal as either a scalar or a vector. If you model the data signal as a vector, set the Sample Packing Dimension to All. In the generated HDL code, the vector elements are packed together and the entire vector is treated as a single sample. You can specify how the data is packed by using the Packing Mode. See Sample Packing Dimension.

Model Data and Valid Signals in Simulink

  1. Enclose the algorithm that processes the Data signal by using an enabled subsystem.

  2. Control the enable port of the enabled subsystem by using the Valid signal.

For example, you can directly connect the Valid signal to the enable port.

You can also use a controller in your DUT that generates an enable signal for the enabled subsystem.

Ready Signal (Optional)

Back pressure is used by downstream components to tell upstream components they are not ready to receive data. The AXI4-Stream interfaces in your DUT can optionally include a Ready signal.. Use the Ready signal to:

  • Apply back pressure in an AXI4-Stream slave interface. For example, drop the Ready signal when the downstream component is not ready to receive data.

  • Respond to back pressure in an AXI4-Stream master interface. For example, stop sending data when the downstream component Ready signal is low.

When you use a single streaming channel, by default, HDL Coder generates the Ready signal and the logic to handle the back pressure. The back pressure logic ties the Ready signal to the DUT Enable signal. When the input master Ready signal is low, the DUT is disabled, and the output slave Ready signal is driven low. Because, HDL Coder generates the back pressure logic and Ready signal, when you use a single streaming channel, the Ready signal is optional and you do not have to model this signal at the DUT port.

Block diagram view illustrating the auto-generated Ready signal and back pressure logic.

When you use multiple streaming channels, HDL Coder generates a ready signal and does not generate the back pressure logic. In a DUT with multiple streaming channels:

  • The master channel ignores the Ready signal from downstream components.

  • The slave channel Ready signal is high which causes upstream components to continue sending data.

The absence of a back pressure logic could result in data being dropped. To avoid data loss and to apply back pressure on the slave interface or respond to back pressure from the master interface in your design:

  • Model the Ready signal for each additional stream interface.

  • Map the modeled Ready signal to a DUT port for the additional interface.

When you do not model the Ready signal, the Set Target Interface task displays a warning that provides names of interfaces that require a Ready port. If your design does not require applying or responding to back pressure, ignore this warning.

If you model the Ready signal in your AXI4-Stream interfaces, your master interface ignores the Data and Valid signals one clock cycle after the Ready signal is de-asserted. You can start sending Data and Valid signals once the Ready signal is asserted. After the Ready signal is de-asserted, you can send one more Data and Valid signal.

If you do not model the Ready signal, HDL Coder generates the signal and the associated back pressure logic. This diagram illustrates the relationship between the Data, Valid, and Ready signals according to the simplified streaming protocol. When you run the IP core generation workflow, HDL Coder adds a streaming interface module in the HDL IP core that translates the simplified protocol to the full AXI4-stream protocol. In this diagram the clock signal is represented by clk.

For example, if you have a first in first out (FIFO) in your DUT to store a frame of data, to apply back pressure to the upstream component, model the Ready signal based on the FIFO Full signal.

Note

If you enable delay balancing, the coder inserts one or more delays on the Ready signal. Disable delay balancing for the Ready signal path.

TLAST Signal (optional)

The AXI4-Stream interface on your DUT can optionally model a TLAST signal, which is used to indicate the end of a frame of data. If you do not model this signal, HDL Coder generates it for you. On the AXI4-Stream Slave interface, the incoming TLAST signal is ignored. On the AXI4-Stream Master interface, the auto-generated TLAST signal is asserted when the number of valid samples counts up to the default frame length value. The default frame length value can be set using the AXI4-Stream interface options in the Target Interface Table. See, Interface Options for AXI4 Stream Data.

When the IP core has an AXI4 Slave interface, the default frame length value is stored in a programable register in the IP core. You can change the default frame length during runtime. When the default frame length register is changed in the middle of a frame, the TLAST counter state is reset to zero and the TLAST signal is asserted early. You can find the address for the programable TLAST register in the IP core generation report.

Frame-Based Modeling

When you want to simulate the data signal as a frame on the DUT boundary, model in frame-based mode. In frame-based mode, model the data signal as a vector and set the Sample Packing Dimension to None. See Sample Packing Dimension.

Frame-based mode is useful for modeling and simulating the system interaction between hardware and software and generating code for the software driver.

Data and Valid Signal Modeling Requirements

When you map vector ports to AXI4-Stream interfaces:

  • Connect each DUT input vector data port to a Serializer1D block.

    The Serializer1D block must have a ValidOut port and the Ratio set to the vector bit width.

  • Connect each DUT output vector data port to a Deserializer1D block.

    The Deserializer1D block must have a ValidIn port and the Ratio set to the vector bit width.

  • Connect each scalar port that maps to an AXI4-Lite interface to a Rate Transition block.

    The ratio in the Rate Transition block must match the ratio in the Serializer1D and Deserializer1D blocks.

  • Each scalar port that maps to an external port must have the same sample time as the streaming algorithm subsystem.

The streaming algorithm subsystem follows the same Data and Valid signal modeling pattern as the pattern for mapping scalar ports to an AXI4-Stream interfaces. See Model Data and Valid Signals in Simulink.

Example

To map vector ports to AXI4-Stream interfaces, open the hdlcoder_sfir_fixed_vector.slx model. In the hdlcoder_sfir_fixed_vector.slx model, the symmetric_fir block is the streaming algorithm subsystem.

Model Designs with Multiple Streaming Channels

When you run the IP Core Generation workflow, you can map multiple scalar DUT ports to AXI4-Stream Master and AXI4-Stream Slave channels. When you use vector ports, you can map the ports to at most one AXI4-Stream Master channel and one AXI4-Stream Slave channel.

Note

If you use multiple streaming channels, HDL Coder generates the Ready signal but does not generate the back pressure logic. If you want your design to handle back pressure, model the Ready signal in your design.

To learn more, see Generate HDL IP Core with Multiple AXI4-Stream and AXI4 Master Interfaces.

Model Designs That Have Multiple Sample Rates

When you run the IP Core Generation workflow, use the HDL Coder software for designs that have multiple sample rates. When you map the interface ports to AXI4-Stream Master or AXI4-Stream Slave interfaces, to use multiple sample rates, map the DUT ports that map to these AXI4 interfaces to run at the fastest rate of the design or at rates slower than the design rate.

HDL Coder runs the DUT ports mapped to AXI4-Stream master and slave interfaces at rates slower than the model design rate by:

  • Setting the AXI4-Stream master channel valid signal to high at the first cycle every N clock cycles. For example, if the design rate is eight times faster than the slow rate DUT ports, the valid signal is high for the first clock cycle every eight clock cycles.

  • Asserting back pressure on the AXI4-Stream slave interface to make sure that the incoming data is streamed at the rate of one data frame every N clock cycles. For example, if the design rate is eight times faster than the slow rate DUT ports, the first frame is streamed at clock cycle one, the second frame at clock cycle nine, and so on.

When you map the AXI4-Stream Interface DUT port to the fastest rate in the design, the valid signal is high always making sure there is no back pressure on the AXI4-Stream slave interface.

When designing models that have multiple sample rates, all AXI4-Stream master interface mapped DUT ports must run at the same rate. All AXI4-Stream slave interface mapped DUT ports must run at the same rate.

To learn more, see Multirate IP Core Generation.

Interface Options for AXI4 Stream Data

When you run the IP Core Generation workflow on a model that has vector data, you can specify how the vector data is treated as a sample or as a frame by using the Sample Packing Dimension. When the vector data is treated as a sample, you can specify how the vector elements are packed together by using the Packing mode option.

When you run the IP Core Generation workflow on a model that has AXI4 Stream interface with none of the signals mapped to TLAST, you can specify the TLAST register value by using the DefaultFrameLength option.

Default Frame Length

Specify the default frame length (TLAST) value for the AXI4 Stream Master interface when you do not model the TLAST signal. The TLAST signal is created for you In the generated IP core and the signal is asserted when the number of valid samples counts up to the value in the default frame length counter. When the generated IP core has an AXI4 Slave interface, HDL Coder generates the default frame length as a programable register. When the default frame length register is changed in the middle of a frame, the TLAST counter state is reset to zero and the TLAST signal is asserted early. For more information, see TLAST Signal (optional). When you do not select the Generate default AXI4 slave interface the default frame length is generated as a constant value and not as a programable register.

Sample Packing Dimension

Specify if the vector data is treated as a sample or as a frame.

  • None. This is the default value. When you specify None, vectors are treated as frames and vector elements are streamed one after the other. For example, when the input is a six-by-one vector in the first clock cycle, the first vector element is streamed, the second vector element, in the second clock cycle, and so on. The model must contain a Serializer block for inputs and a Deserializer block for the outputs to use this mode. The Packing mode is not available when the Sample Packing Dimension is set to None.

  • All. When you specify All , the vectors are packed together and streamed in a single clock cycle. For example, when the input is a six-by-one vector all vector elements are packed together and streamed in a single clock cycle. In this case, you can specify how the vector elements are packed by using the Packing mode option.

Packing Mode

Specify how vector elements are packed together when the Sample Packing Dimension is set to All. The packing mode applies to the AXI4-Stream slave and master channels. On the master channel, the data is packed using the Bit Aligned or Power of 2 Aligned formats. On the slave channel, the data is unpacked based on the master channel packing format.

  • Bit Aligned. In this mode the vector elements are packed directly next to each other. If the packed bit width is less than the AXI4-Stream channel width, then the packed data is padded with zeros to match the channel width.

    For example:

    • AXI4-Stream channel width is 256 bits.

    • Vectors are 30 bits long and there are 4 vector frames. The total data width is 120 bits.

    When the packing mode is set to Bit Aligned , the AXI4-Stream data is packed as in this diagram

    zero padded bit aligned vector data

  • Power of 2 Aligned. In this mode, the vector elements are first padded with zeros to the closest power of two boundary. Then, the padded elements are packed together. If the packed vector bit width is less than the AXI4-Stream channel width, then the packed data is padded with zeros to match the channel width.

    For example:

    • AXI4-Stream channel width is 256 bits.

    • Vectors are 30 bits long and there are 4 vector frames. The total data width is 120 bits.

    When the packing mode is set to Power of 2 Aligned the AXI4-Stream data is packed as shown in this diagram:

    power of 2 packed vector data

    Each vector element of bit width 30 is padded with zeros of bit width two to extend it to 32, the nearest power of two boundary.

Restrictions

When you map scalar or vector DUT ports to AXI4-Stream interfaces:

  • Xilinx® Zynq®-7000 or Intel® Quartus® Prime must be your target platform.

  • Xilinx Vivado® or Intel Quartus Prime must be your synthesis tool.

  • Processor/FPGA synchronization must be Free Running.

When you use frame-based modeling, you cannot use protocol signals other than Data and Valid. For example, Ready and TLAST are not supported.

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