Optimization Basics

Hierarchy flattening, delay balancing, validation model, constrained overclocking, and feedback loop highlighting

Optimize your design for a target FPGA or SoC device by applying optimizations such as hierarchy flattening, delay balancing, or feedback loop highlighting. Applying base optimizations helps to generate more hardware-efficient HDL code and properly simulate the generated code.

Checks

Check delay balancing setting

Topics

Speed and Area Optimizations in HDL Coder
Learn about various speed and area optimizations and how to optimize your design.
Find Feedback Loops
Highlight feedback loops that are inhibiting optimizations.
Hierarchy Flattening
Flatten subsystem hierarchy to enable more extensive area and speed optimization.
Optimization with Constrained Overclocking
Optimization with constrained overclocking and how it works.
Understand Delay Balancing in HDL Coder
Insert matching delays along data paths.
Use Delay Absorption While Modeling with Latency
Model with latency to absorb design delays and prevent a timing mismatch between the original and generated model.
Generated Model and Validation Model
The generated model is a model created during HDL code generation that shows the HDL implementation architecture and includes latency.
Remove Redundant Logic and Unused Blocks in Generated HDL Code
Improve readability of generated HDL code and optimize area usage.
Optimize Unconnected Ports in HDL Code for Simulink Models
Optimize unused ports in generated HDL code in combination with redundant logic deletion.
Simplify Constant Operations and Reduce Design Complexity in HDL Coder
Area and timing optimizations that simplify constants and optimize mathematical operations.
Meet Timing Requirements Using Enable-Based Multicycle Path Constraints
Generate enable-based constraints for synthesis tools to meet timing requirements of multicycle paths in single clock mode.
Iteratively Meet Timing Requirements Using Multicycle Path Constraints for Cadence Genus
Use multicycle path constraints with HDL Workflow Advisor and Cadence Genus synthesis tools to meet the timing requirements for ASIC devices.

Troubleshooting

Resolve Delays Not Absorbed During Delay Balancing

Troubleshoot extra latency not absorbed during HDL code generation.

Featured Examples

Investigate and Resolve Non-Absorbable Latency

Recommendations for troubleshooting common delay balancing issues.

Open Live Script

Delay Balancing and Validation Model Workflow in HDL Coder

How HDL Coder™ can automatically balance delays within a model. HDL Coder may introduce additional delays in the HDL implementation for a given model. These delays may be introduced by either certain block implementations or by optimizations for the purpose of improving the efficiency of the hardware implementations. However, introducing delays on only certain paths can result functional behavior that is different from the original intent of the user model, thereby violating functional equivalence between the original user model and the HDL implementation.

Open Script

Control the Scope of Delay Balancing

Balance delays in specific parts of a design, without balancing delays on the entire design.

Open Script

Use Multicycle Path Constraints to Meet Timing for Slow Paths

Apply multicycle path constraints in your design to meet timing requirements. Using multicycle path constraints can save area and reduce synthesis run times. For more information, see Meet Timing Requirements Using Enable-Based Multicycle Path Constraints.

Open Script

Delay Balancing on Multirate Designs

Recommendations for optimal code generation of a multirate design.

Open Script

How useful was this information?

Unrated 1 star 2 stars 3 stars 4 stars 5 stars