HDL Code Generation

Generate HDL code from MATLAB^® and Simulink^®

To implement a DSP design on FPGAs or ASICs, you can use either HDL Coder™ or Filter Design HDL Coder™. Both products generate synthesizable and portable VHDL^® and Verilog^® code, and also generate VHDL and Verilog test benches for quickly simulating, testing, and verifying the generated code.

HDL Coder — Generate code from Simulink or MATLAB designs. Supported blocks in DSP System Toolbox™ and DSP HDL Toolbox include filters, math and signal operations, and other algorithms optimized for resource use and performance, such as the FFT (DSP HDL Toolbox), Discrete FIR Filter (DSP HDL Toolbox), and NCO (DSP HDL Toolbox) blocks. For a basic example of how to generate HDL code using HDL Coder, see Programmable FIR Filter for FPGA. For an introduction to DSP HDL Toolbox™, see Implement FFT Algorithm for FPGA (DSP HDL Toolbox).
Filter Design HDL Coder — Generate code from MATLAB filter designs. You can access code and test bench generation features using the Generate HDL user interface, or by using command-line options. These features are also integrated with the Filter Designer app. For an example of how to generate HDL code using Filter Design HDL Coder, see HDL Butterworth Filter (Filter Design HDL Coder).

To debug your designs in Simulink or MATLAB, use the Logic Analyzer waveform viewer.

Simulink Visualization Tool

Logic Analyzer

Visualize, measure, and analyze transitions and states over time

Topics

Find Blocks That Support HDL Code Generation
Filter for blocks that support HDL code generation in the Simulink library browser and in documentation.
High-Throughput HDL Algorithms (DSP HDL Toolbox)
Choose a block that supports frame-based processing for HDL code generation.
HDL Filter Architectures
HDL code generation parameters to control speed and area tradeoffs in filter architectures.
Subsystem Optimizations for Filters
Select resource sharing and pipeline optimization options.
Visualizing Multiple Signals Using Logic Analyzer
Visualize multiple signals of a programmable FIR filter by using a logic analyzer.
Generate HDL Code for Filter System Objects (Filter Design HDL Coder)
Learn about the specifics of HDL code generation from filter System objects.

Related Information

DSP HDL Toolbox

Featured Examples

Programmable FIR Filter for FPGA

Implement a programmable FIR filter for hardware. You can program the filter to the required response by loading the coefficients into internal registers using a memory-style interface.

Open Model

Multichannel FIR Filter for FPGA

Implement a discrete FIR filter with multiple input data streams for hardware.

Open Script

Optimized Fixed-Point FIR Filters

Optimize fixed-point FIR filters. The optimization can refer to the characteristics of the filter response such as the stopband attenuation or the number of bits required to achieve a particular specification. This functionality is particularly useful for users targeting hardware that have a number of configurable coefficients of a specific wordlength and/or in cases typically found on ASICs and FPGAs where there is a large design space to explore. A hardware designer can usually trade off more coefficients for less bits or vice-versa to optimize for different ASICs or FPGAs.

Open Live Script

Implement Digital Downconverter for FPGA

Design a digital downconverter (DDC) for radio communication applications such as LTE, and generate HDL code.

Open Script

Implement Digital Upconverter for FPGA

Design a digital upconverter (DUC) for radio communication applications such as LTE, and generate HDL code.

Open Script