Functional verification typically consumes the largest amount of time and resources on ASIC, SoC FPGA, and FPGA design projects. To improve efficiency, verification teams are adopting Accellera’s Universal Verification Methodology (UVM) standard along with IEEE Standard 1800 SystemVerilog (refer to: Latest Blog Blog Part 6 and Blog Part 10).
The main goal behind this approach is to increase verification efficiency through reusable verification components. However, manually creating and debugging UVM verification components still requires a significant amount of effort (refer to: Blog Part 8).
Since many chip design projects begin as algorithms in MATLAB® or Simulink®, test bench development efforts can be reduced by reusing the MATLAB code or Simulink models in the UVM verification environment.
HDL Verifier™ can automatically generate a SystemVerilog DPI component from MATLAB code or Simulink models. This component can be used as a golden reference checker model in a UVM verification scoreboard, as a behavioral digital or analog component model in mixed-signal simulation, or as a sequence item in your UVM verification stimulus.
HDL Verifier can also generate UVM components directly from Simulink models. HDL Verifier generates SystemVerilog UVM sequence and scoreboard components from models of test benches. It also produces SystemVerilog files for a behavioral design under test (DUT). The behavioral DUT can then be replaced with hand-coded RTL or with RTL generated using HDL Coder.
The generated components can run as a complete UVM environment in Mentor Graphics® ModelSim® or Questa®, Cadence® Xcelium™, or Synopsys® VCS®. Alternatively, the generated components can be incorporated into existing UVM environments.
For additional information, see HDL Verifier.