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Using Qualified Tools in a DO-178C Development Process, Part 5: Qualified Model Verification – Design Errors

From the series: Using Qualified Tools in a DO-178C Development Process

Bill Potter, MathWorks

Showing accuracy and consistency of low-level requirements and software architecture is an objective in DO-178C. When using formal methods, DO-333 allows these objectives to be satisfied by formal analysis, which can be applied when using models for the design. Simulink Design Verifier™ is a tool that can perform formal analysis on Simulink^® and Stateflow^®models. One of the formal analysis features of Simulink Design Verifier is design error detection, which detects certain potential run-time errors in the design model. The types of errors that can be detected in the model are: dead logic, integer overflows, division by zero, exceeding specified minimum and maximum values of signals, and out-of-bound array accesses. The analysis for dead logic must be run separately from the other defects. A dead logic report is generated for the model and will indicate any areas of the model that have unreachable logic, thus indicating a design error. The report will clearly show the model elements that are part of the dead logic. The other possible defects can all be analyzed in a single analysis run, with a combined report being generated for those potential errors. This report also clearly shows the model elements where the specific errors can occur. The DO Qualification Kit provides the necessary artifacts to qualify design error detection and reporting by Simulink Design Verifier. The kit also provides the evidence necessary to show soundness of the formal method, as required by DO-333.

Product Focus

Series: Using Qualified Tools in a DO-178C Development Process

Part 1: Introduction to Model-Based Development for DO-178C Learn how to use of Model-Based Design and formal methods with Simulink, Stateflow, Embedded Coder, and the DO Qualification Kit in a process compliant with DO-178C, DO-331, DO-333, and DO-330.

Part 2: Qualified Model Verification – Requirements Tracing Perform tracing from models to requirements, in compliance with DO-178C and DO-331, using Simulink Requirements, and then generate a design description document using Simulink Report Generator.

Part 3: Qualified Model Verification – Simulation Perform simulation and model coverage analysis to verify models, in compliance with DO-178C and DO-331, using Simulink Test and Simulink Coverage.

Part 4: Qualified Model Verification – Model Standards Perform static analysis to verify model standards, consistency, and accuracy, in compliance with DO-178C and DO-331, using Simulink Check.

Part 5: Qualified Model Verification – Design Errors Perform formal methods analysis to verify model consistency and accuracy, in compliance with DO-178C and DO-333, using Simulink Design Verifier.

Part 6: Qualified Code Verification – Model To Code Use Embedded Coder and Simulink Code Inspector to generate code from models and verify that translation in compliance with DO-178C and DO-331.

Part 7: Qualified Code Verification – Code Standards Use Embedded Coder and Polyspace Bug Finder to generate code from models and verify coding standards in compliance with DO-178C and DO-331.

Part 8: Qualified Code Verification – Code Errors Perform formal methods analysis to verify code consistency and accuracy, in compliance with DO-178C and DO-333, using Polyspace Code Prover.

Part 9: Qualified Test Generation Use Simulink Design Verifier and Simulink Coverage to generate tests from models and verify low-level test coverage, in compliance with DO-178C and DO-331.

Part 10: Qualified Software Testing Use processor-in-the-loop capability and code coverage analysis to verify executable object code, in compliance with DO-178C and DO-331, with Simulink Test and Simulink Coverage.

Part 11: Tool Qualification Qualify MathWorks tools in compliance with DO-178C and DO-330 using the DO Qualification Kit.

Related Products

DO Qualification Kit

Learn more about the DO Qualification Kit

Next in Series

Part 6: Qualified Code Verification – Model To Code

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