Answered
Problems occur when both simulink HDL blocks and vivado HLS blocks are used to generate HDL code.
https://www.mathworks.com/help/hdlcoder/ug/using-xilinx-system-generator-for-dsp-with-hdl-coder.html

4 years ago | 0

Answered
results of HDL streaming FFT block is not same as FFt block in dsp toolbox
dsp.HDLFFT is optimized for HDL Code generation. dsp.HDLFFT Fast Fourier transform — optimized for HDL code generation The H...

4 years ago | 0

Answered
Potential Bugs in R2014b HDL Coder ('hdlcoder_slsysgen')
https://www.mathworks.com/help/hdlcoder/ug/using-xilinx-system-generator-for-dsp-with-hdl-coder.html

4 years ago | 0

Answered
Generating higher sampling frequency
Using Oversampling Factor and Latency Strategy The Oversampling factor (HDL Coder) specifies the factor by which the FPGA clock...

4 years ago | 0

Answered
GPU: Audio DSP
https://www.mathworks.com/help/hdlcoder/ug/running-an-audio-filter-on-live-audio-input-using-a-zynq-board.html

4 years ago | 0

| accepted

Answered
Can Matlab R2018b use the Kintex7 board from a X310 USRP and, if so, how?
https://www.mathworks.com/hardware-support/usrp.html

4 years ago | 0

Answered
FPGA: Audio DSP
Running an Audio Filter on Live Audio Input Using a Zynq Board This example shows how to model an audio system and implement it...

4 years ago | 0

| accepted

Answered
Error while converting a sine PWM block in simulink to HDL code
See the attached example on how to generate square wave pulses at regular intervals. The waveform parameters, Amplitude, Pulse W...

4 years ago | 0

Answered
Error while converting a sine PWM block in simulink to HDL code

4 years ago | 0

Answered
Having issues with connecting Zynq zedboard to computer
web(fullfile(docroot, 'hdlcoder/ug/define-and-register-custom-board-and-reference-design-for-zynq-workflow.html'))

4 years ago | 0

Answered
I want to know about the resource utilization on a FPGA when using FFT HDL code generated by HDL coder application on MATLAB.
web(fullfile(docroot, 'dsp/ref/ffthdloptimized.html?s_tid=doc_ta')) Check Performance section

4 years ago | 0

Answered
How does it work the AXI4 Stream IIO driver?
web(fullfile(docroot, 'hdlcoder/ug/getting-started-with-axi4-stream-interface-in-zynq-workflow.html?s_tid=doc_srchtitle')) we...

4 years ago | 0

Answered
Best Practices for Simulink HDL Coder Development
https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-reference-guide HDL Coder Evaluation Referenc...

4 years ago | 0

Answered
HDL Coder (2014b) fixed point division RoundMode error
Consider using hdlfimath when generating HDL code from MATLAB with fixed-point. >> hdlfimath

4 years ago | 0

Answered
Does HDL coder from Simulink support AXI-4 Stream Interface for Xilinx Zynq?
Getting Started with AXI4-Stream Interface in Zynq Workflow This example uses: HDL Coder DSP System Toolbox Embedded Coder...

4 years ago | 0

Answered
Strange behavior of HDL coder when generating resettable register
Synchronous Subsystem Behavior with the State Control Block What Is a State Control Block? When you have blocks with state, ...

4 years ago | 0

Answered
I have the following errors when I run HDL coder in MATLAB 2013a ?errors in fixed point conversion
This is an unexpected internal error during fixed-point conversion. The issue occurs during verification step of generated fixed...

4 years ago | 0

Answered
How to prepare FPGA board for MATLAB
You would need license to HDL Coder. See third party tool requirements for HDL Coder in this page. web(fullfile(docroot, 'hdlc...

4 years ago | 0

Answered
Is it possible to purge Simulink Model?
attached sample file can be extended to purge whatever cruft you have in your session. >> purgesession Purging slprj Purging ...

4 years ago | 0

Answered
Simulation of matlab generated vhdl code leads to Errors
HDL Coder handles MATLAB one based indexing and converts the logic to zero based indexing when generating VHDL / Verilog code. ...

4 years ago | 0

Answered
HDL Coder with Xilinx Sysgen R2013b
Using Xilinx® System Generator for DSP with HDL Coder™ This example shows how to use Xilinx System Generator for DSP with HDL C...

4 years ago | 0

Answered
Hi sir i am working on hdl coder and i am new to it and my pbm is have written the matlab code and compiled it sucessfully, even generated hdl code but in hdl test bench i am not getting the exact ans( matlab output and hdl output not matching).
HDL Coder generates bit true and cycle accurate code corresponding to the design. The testbench captures the stimulus and respon...

4 years ago | 0

Answered
sir I want to convert my .m file to VHDL . my code is given below.
You need to break the design into two parts. A testbench and a design. Follow basic example shown here. >> mlhdlc_demo_setup('...

4 years ago | 0

Answered
How to do area optimization(sharing and streaming) with feedback loop like that AGC or AFC in communication system?
To address pipelining of blocks in feedback loops you can refer to this example and related HDL Coder features. https://www.mat...

4 years ago | 0

Answered
I want to generate hdl code using Matlab simulink. But getting a error, I have attached my Matlab Code. please help
You have to break the script into design and testbench. See basic examples in the documentation. >> mlhdlc_demo_setup('sfir') ...

4 years ago | 0

Answered
Suggest a good reference book for Simulink and/or MATLAB to HDL Code converter
HDL Code Generation from MATLAB Generate HDL Code from MATLAB® algorithms Implement your MATLAB algorithm in hardware by gen...

4 years ago | 0

Answered
how can i solve the message below?
see example usage in HDL Code Generation from System Objects

4 years ago | 0

Answered
ROM block generated by HDL Coder not inferred by Vivado Synthesis tool
It is possible LUT size in your model does not meet the threshold for ROM mapping on the synthesis tool. Try the example belo...

4 years ago | 0

Answered
How do I convert matlab code to VHDL in matlab 15?
Try basic MATLAB to HDL examples. mlhdlc_demo_setup('sfir') mlhdlc_demo_setup('heq')

4 years ago | 0

Answered
HDL Coder generates VHD Files for Sample and Hold Blocks
Attached model has several Sample and Hold Blocks in addition to Sin function configured to use CORDIC architecture. The fla...

4 years ago | 0