Adriaan Sadie

Last seen: meer dan 4 jaar ago | Active since 2018

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How do I add FPGA data capture IP core in existing Vivado project?
I am using the FPGA data capture component from Matlab (generateFPGADataCaptureIP) to generate a logic analyzer IP core which I ...

ongeveer 5 jaar ago | 2 answers | 0

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How can I access future samples of a discrete time signal in Simulink?
Hi I am busy with a project that implements model predictive control and it uses a reference signal's future sample values, i...

meer dan 6 jaar ago | 0 answers | 0

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