Statistics
RANK
290.188
of 299.737
REPUTATION
0
CONTRIBUTIONS
2 Questions
1 Answer
ANSWER ACCEPTANCE
50.0%
VOTES RECEIVED
0
RANK
of 20.791
REPUTATION
N/A
AVERAGE RATING
0.00
CONTRIBUTIONS
0 Files
DOWNLOADS
0
ALL TIME DOWNLOADS
0
RANK
of 165.655
CONTRIBUTIONS
0 Problems
0 Solutions
SCORE
0
NUMBER OF BADGES
0
CONTRIBUTIONS
0 Posts
CONTRIBUTIONS
0 Public Channels
AVERAGE RATING
CONTRIBUTIONS
0 Highlights
AVERAGE NO. OF LIKES
Feeds
Using Unit Delays in triggered Subsystems for HDL Codegeneration
I solved the problem. I had a Limited Counter for triggering the subsystem. After replacing it by an HDL counter, everything i...
bijna 8 jaar ago | 0
| accepted
Question
Using Unit Delays in triggered Subsystems for HDL Codegeneration
Hi, i'm having some Unit Delays in a Triggered Subsystem. When generating VHDL Code using Mathworks HDL Coder I get the foll...
bijna 8 jaar ago | 2 answers | 0
2
answersQuestion
HDL Coder generates VHD Files for Sample and Hold Blocks
Hi, I'm using Sample and Hold Blocks in my design. When I generate the VHDL Code, I get files named like "controlss_block.vhd"...
meer dan 8 jaar ago | 1 answer | 0
